1/* 2 * Copyright (c) 2010, 2012-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1384 unchanged lines hidden (view full) --- 1393 case 0x4: // Normal memory, Outer Non-cacheable 1394 case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 1395 te.nonCacheable = true; 1396 } 1397 switch (attr_lo) { 1398 case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 1399 case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 1400 warn_if(!attr_hi, "Unpredictable behavior"); |
1401 M5_FALLTHROUGH; |
1402 case 0x4: // Device-nGnRE memory or 1403 // Normal memory, Inner Non-cacheable 1404 case 0x8: // Device-nGRE memory or 1405 // Normal memory, Inner Write-through non-transient 1406 te.nonCacheable = true; 1407 } 1408 1409 te.shareable = sh == 2; --- 859 unchanged lines hidden --- |