1/* |
2 * Copyright (c) 2010, 2012-2017 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 1326 unchanged lines hidden (view full) --- 1337 te.innerAttrs = attr_lo == 0 ? 1 : 3; 1338 te.nonCacheable = true; 1339 } else { 1340 te.mtype = TlbEntry::MemoryType::Normal; 1341 te.outerAttrs = attr_hi == 1 ? 0 : 1342 attr_hi == 2 ? 2 : 1; 1343 te.innerAttrs = attr_lo == 1 ? 0 : 1344 attr_lo == 2 ? 6 : 5; |
1345 // Treat write-through memory as uncacheable, this is safe 1346 // but for performance reasons not optimal. 1347 te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) || 1348 (attr_lo == 1) || (attr_lo == 2); |
1349 } 1350 } else { 1351 uint8_t attrIndx = lDescriptor.attrIndx(); 1352 1353 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh); 1354 1355 // Select MAIR 1356 uint64_t mair; --- 18 unchanged lines hidden (view full) --- 1375 attr_lo = bits(attr, 3, 0); 1376 attr_hi = bits(attr, 7, 4); 1377 1378 // Memory type 1379 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal; 1380 1381 // Cacheability 1382 te.nonCacheable = false; |
1383 if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory |
1384 te.nonCacheable = true; 1385 } |
1386 // Treat write-through memory as uncacheable, this is safe 1387 // but for performance reasons not optimal. 1388 switch (attr_hi) { 1389 case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 1390 case 0x4: // Normal memory, Outer Non-cacheable 1391 case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient 1392 te.nonCacheable = true; 1393 } 1394 switch (attr_lo) { 1395 case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient 1396 case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient 1397 warn_if(!attr_hi, "Unpredictable behavior"); 1398 case 0x4: // Device-nGnRE memory or 1399 // Normal memory, Inner Non-cacheable 1400 case 0x8: // Device-nGRE memory or 1401 // Normal memory, Inner Write-through non-transient 1402 te.nonCacheable = true; 1403 } |
1404 1405 te.shareable = sh == 2; 1406 te.outerShareable = (sh & 0x2) ? true : false; 1407 // Attributes formatted according to the 64-bit PAR 1408 te.attributes = ((uint64_t) attr << 56) | 1409 (1 << 11) | // LPAE bit 1410 (te.ns << 9) | // NS bit 1411 (sh << 7); --- 853 unchanged lines hidden --- |