2c2
< * Copyright (c) 2010, 2012-2016 ARM Limited
---
> * Copyright (c) 2010, 2012-2017 ARM Limited
1345c1345,1348
< te.nonCacheable = (attr_hi == 1) || (attr_lo == 1);
---
> // Treat write-through memory as uncacheable, this is safe
> // but for performance reasons not optimal.
> te.nonCacheable = (attr_hi == 1) || (attr_hi == 2) ||
> (attr_lo == 1) || (attr_lo == 2);
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< if (te.mtype == TlbEntry::MemoryType::Device || // Device memory
< attr_hi == 0x8 || // Normal memory, Outer Non-cacheable
< attr_lo == 0x8) { // Normal memory, Inner Non-cacheable
---
> if (te.mtype == TlbEntry::MemoryType::Device) { // Device memory
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> // Treat write-through memory as uncacheable, this is safe
> // but for performance reasons not optimal.
> switch (attr_hi) {
> case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient
> case 0x4: // Normal memory, Outer Non-cacheable
> case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient
> te.nonCacheable = true;
> }
> switch (attr_lo) {
> case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
> case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
> warn_if(!attr_hi, "Unpredictable behavior");
> case 0x4: // Device-nGnRE memory or
> // Normal memory, Inner Non-cacheable
> case 0x8: // Device-nGRE memory or
> // Normal memory, Inner Write-through non-transient
> te.nonCacheable = true;
> }