252c252,255
< switch (currState->el) {
---
> if (isStage2) {
> currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
> currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
> } else switch (currState->el) {
271a275
> currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
292,294c296,297
< // @todo: for now disable this in AArch64 (HCR is not set)
< currState->stage2Req = !currState->aarch64 && currState->hcr.vm &&
< !isStage2 && !currState->isSecure && !currState->isHyp;
---
> currState->stage2Req = currState->hcr.vm && !isStage2 &&
> !currState->isSecure && !currState->isHyp;
745a749,751
>
> LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
>
749c755,774
< switch (bits(currState->vaddr, 63,48)) {
---
> if (isStage2) {
> DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
> ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
> tsz = 64 - currState->vtcr.t0sz64;
> tg = GrainMapDefault[currState->vtcr.tg0];
> // ARM DDI 0487A.f D7-2148
> // The starting level of stage 2 translation depends on
> // VTCR_EL2.SL0 and VTCR_EL2.TG0
> LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
> uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
> static const LookupLevel SLL[] = {
> L2, L3, L3, __, // sl0 == 0
> L1, L2, L2, __, // sl0 == 1, etc.
> L0, L1, L1, __,
> __, __, __, __
> };
> start_lookup_level = SLL[sl_tg];
> panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
> "Cannot discern lookup level from vtcr.{sl0,tg0}");
> } else switch (bits(currState->vaddr, 63,48)) {
827,829d851
< int stride = tg - 3;
< LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
<
836c858
< {
---
> if (start_lookup_level == MAX_LOOKUP_LEVELS) {
866a889,890
> int stride = tg - 3;
>
972,975c996,998
< port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
< NULL, (uint8_t*) &currState->longDesc.data,
< currState->tc->getCpuPtr()->clockPeriod(), flag);
< doLongDescriptor();
---
> fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
> sizeof(uint64_t), flag, -1, NULL,
> &TableWalker::doLongDescriptor);
1916,1917c1939,1944
< // do the requests for the page table descriptors have to go through the
< // second stage MMU
---
> DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n",
> descAddr, currState->stage2Req);
>
> // If this translation has a stage 2 then we know descAddr is an IPA and
> // needs to be translated before we can access the page table. Do that
> // check here.