table_walker.cc (14095:4f5d16d7cf45) | table_walker.cc (14280:9e3f2937f72c) |
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1/* 2 * Copyright (c) 2010, 2012-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 443 unchanged lines hidden (view full) --- 452 453Fault 454TableWalker::processWalk() 455{ 456 Addr ttbr = 0; 457 458 // If translation isn't enabled, we shouldn't be here 459 assert(currState->sctlr.m || isStage2); | 1/* 2 * Copyright (c) 2010, 2012-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 443 unchanged lines hidden (view full) --- 452 453Fault 454TableWalker::processWalk() 455{ 456 Addr ttbr = 0; 457 458 // If translation isn't enabled, we shouldn't be here 459 assert(currState->sctlr.m || isStage2); |
460 const bool is_atomic = currState->req->isAtomic(); |
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460 461 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 462 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 463 32 - currState->ttbcr.n)); 464 465 statWalkWaitTime.sample(curTick() - currState->startTime); 466 467 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, --- 5 unchanged lines hidden (view full) --- 473 return std::make_shared<PrefetchAbort>( 474 currState->vaddr_tainted, 475 ArmFault::TranslationLL + L1, 476 isStage2, 477 ArmFault::VmsaTran); 478 else 479 return std::make_shared<DataAbort>( 480 currState->vaddr_tainted, | 461 462 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n", 463 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31, 464 32 - currState->ttbcr.n)); 465 466 statWalkWaitTime.sample(curTick() - currState->startTime); 467 468 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31, --- 5 unchanged lines hidden (view full) --- 474 return std::make_shared<PrefetchAbort>( 475 currState->vaddr_tainted, 476 ArmFault::TranslationLL + L1, 477 isStage2, 478 ArmFault::VmsaTran); 479 else 480 return std::make_shared<DataAbort>( 481 currState->vaddr_tainted, |
481 TlbEntry::DomainType::NoAccess, currState->isWrite, | 482 TlbEntry::DomainType::NoAccess, 483 is_atomic ? false : currState->isWrite, |
482 ArmFault::TranslationLL + L1, isStage2, 483 ArmFault::VmsaTran); 484 } 485 ttbr = currState->tc->readMiscReg(snsBankedIndex( 486 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 487 } else { 488 DPRINTF(TLB, " - Selecting TTBR1\n"); 489 // Check if table walk is allowed when Security Extensions are enabled 490 if (haveSecurity && currState->ttbcr.pd1) { 491 if (currState->isFetch) 492 return std::make_shared<PrefetchAbort>( 493 currState->vaddr_tainted, 494 ArmFault::TranslationLL + L1, 495 isStage2, 496 ArmFault::VmsaTran); 497 else 498 return std::make_shared<DataAbort>( 499 currState->vaddr_tainted, | 484 ArmFault::TranslationLL + L1, isStage2, 485 ArmFault::VmsaTran); 486 } 487 ttbr = currState->tc->readMiscReg(snsBankedIndex( 488 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 489 } else { 490 DPRINTF(TLB, " - Selecting TTBR1\n"); 491 // Check if table walk is allowed when Security Extensions are enabled 492 if (haveSecurity && currState->ttbcr.pd1) { 493 if (currState->isFetch) 494 return std::make_shared<PrefetchAbort>( 495 currState->vaddr_tainted, 496 ArmFault::TranslationLL + L1, 497 isStage2, 498 ArmFault::VmsaTran); 499 else 500 return std::make_shared<DataAbort>( 501 currState->vaddr_tainted, |
500 TlbEntry::DomainType::NoAccess, currState->isWrite, | 502 TlbEntry::DomainType::NoAccess, 503 is_atomic ? false : currState->isWrite, |
501 ArmFault::TranslationLL + L1, isStage2, 502 ArmFault::VmsaTran); 503 } 504 ttbr = currState->tc->readMiscReg(snsBankedIndex( 505 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 506 currState->ttbcr.n = 0; 507 } 508 --- 77 unchanged lines hidden (view full) --- 586 (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 587 else 588 ttbr0_max = (1ULL << 32) - 1; 589 if (currState->ttbcr.t1sz) 590 ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 591 else 592 ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 593 | 504 ArmFault::TranslationLL + L1, isStage2, 505 ArmFault::VmsaTran); 506 } 507 ttbr = currState->tc->readMiscReg(snsBankedIndex( 508 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 509 currState->ttbcr.n = 0; 510 } 511 --- 77 unchanged lines hidden (view full) --- 589 (1ULL << (32 - currState->ttbcr.t1sz)) - 1; 590 else 591 ttbr0_max = (1ULL << 32) - 1; 592 if (currState->ttbcr.t1sz) 593 ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz)); 594 else 595 ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz)); 596 |
597 const bool is_atomic = currState->req->isAtomic(); 598 |
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594 // The following code snippet selects the appropriate translation table base 595 // address (TTBR0 or TTBR1) and the appropriate starting lookup level 596 // depending on the address range supported by the translation table (ARM 597 // ARM issue C B3.6.4) 598 if (currState->vaddr <= ttbr0_max) { 599 DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 600 // Check if table walk is allowed 601 if (currState->ttbcr.epd0) { 602 if (currState->isFetch) 603 return std::make_shared<PrefetchAbort>( 604 currState->vaddr_tainted, 605 ArmFault::TranslationLL + L1, 606 isStage2, 607 ArmFault::LpaeTran); 608 else 609 return std::make_shared<DataAbort>( 610 currState->vaddr_tainted, 611 TlbEntry::DomainType::NoAccess, | 599 // The following code snippet selects the appropriate translation table base 600 // address (TTBR0 or TTBR1) and the appropriate starting lookup level 601 // depending on the address range supported by the translation table (ARM 602 // ARM issue C B3.6.4) 603 if (currState->vaddr <= ttbr0_max) { 604 DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n"); 605 // Check if table walk is allowed 606 if (currState->ttbcr.epd0) { 607 if (currState->isFetch) 608 return std::make_shared<PrefetchAbort>( 609 currState->vaddr_tainted, 610 ArmFault::TranslationLL + L1, 611 isStage2, 612 ArmFault::LpaeTran); 613 else 614 return std::make_shared<DataAbort>( 615 currState->vaddr_tainted, 616 TlbEntry::DomainType::NoAccess, |
612 currState->isWrite, | 617 is_atomic ? false : currState->isWrite, |
613 ArmFault::TranslationLL + L1, 614 isStage2, 615 ArmFault::LpaeTran); 616 } 617 ttbr = currState->tc->readMiscReg(snsBankedIndex( 618 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 619 tsz = currState->ttbcr.t0sz; 620 if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB --- 7 unchanged lines hidden (view full) --- 628 currState->vaddr_tainted, 629 ArmFault::TranslationLL + L1, 630 isStage2, 631 ArmFault::LpaeTran); 632 else 633 return std::make_shared<DataAbort>( 634 currState->vaddr_tainted, 635 TlbEntry::DomainType::NoAccess, | 618 ArmFault::TranslationLL + L1, 619 isStage2, 620 ArmFault::LpaeTran); 621 } 622 ttbr = currState->tc->readMiscReg(snsBankedIndex( 623 MISCREG_TTBR0, currState->tc, !currState->isSecure)); 624 tsz = currState->ttbcr.t0sz; 625 if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB --- 7 unchanged lines hidden (view full) --- 633 currState->vaddr_tainted, 634 ArmFault::TranslationLL + L1, 635 isStage2, 636 ArmFault::LpaeTran); 637 else 638 return std::make_shared<DataAbort>( 639 currState->vaddr_tainted, 640 TlbEntry::DomainType::NoAccess, |
636 currState->isWrite, | 641 is_atomic ? false : currState->isWrite, |
637 ArmFault::TranslationLL + L1, 638 isStage2, 639 ArmFault::LpaeTran); 640 } 641 ttbr = currState->tc->readMiscReg(snsBankedIndex( 642 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 643 tsz = currState->ttbcr.t1sz; 644 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB --- 5 unchanged lines hidden (view full) --- 650 currState->vaddr_tainted, 651 ArmFault::TranslationLL + L1, 652 isStage2, 653 ArmFault::LpaeTran); 654 else 655 return std::make_shared<DataAbort>( 656 currState->vaddr_tainted, 657 TlbEntry::DomainType::NoAccess, | 642 ArmFault::TranslationLL + L1, 643 isStage2, 644 ArmFault::LpaeTran); 645 } 646 ttbr = currState->tc->readMiscReg(snsBankedIndex( 647 MISCREG_TTBR1, currState->tc, !currState->isSecure)); 648 tsz = currState->ttbcr.t1sz; 649 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB --- 5 unchanged lines hidden (view full) --- 655 currState->vaddr_tainted, 656 ArmFault::TranslationLL + L1, 657 isStage2, 658 ArmFault::LpaeTran); 659 else 660 return std::make_shared<DataAbort>( 661 currState->vaddr_tainted, 662 TlbEntry::DomainType::NoAccess, |
658 currState->isWrite, ArmFault::TranslationLL + L1, | 663 is_atomic ? false : currState->isWrite, 664 ArmFault::TranslationLL + L1, |
659 isStage2, ArmFault::LpaeTran); 660 } 661 662 } 663 664 // Perform lookup (ARM ARM issue C B3.6.6) 665 if (start_lookup_level == L1) { 666 n = 5 - tsz; --- 177 unchanged lines hidden (view full) --- 844 default: 845 // invalid addr if top two bytes are not all 0s 846 fault = true; 847 } 848 ps = currState->tcr.ps; 849 break; 850 } 851 | 665 isStage2, ArmFault::LpaeTran); 666 } 667 668 } 669 670 // Perform lookup (ARM ARM issue C B3.6.6) 671 if (start_lookup_level == L1) { 672 n = 5 - tsz; --- 177 unchanged lines hidden (view full) --- 850 default: 851 // invalid addr if top two bytes are not all 0s 852 fault = true; 853 } 854 ps = currState->tcr.ps; 855 break; 856 } 857 |
858 const bool is_atomic = currState->req->isAtomic(); 859 |
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852 if (fault) { 853 Fault f; 854 if (currState->isFetch) 855 f = std::make_shared<PrefetchAbort>( 856 currState->vaddr_tainted, 857 ArmFault::TranslationLL + L0, isStage2, 858 ArmFault::LpaeTran); 859 else 860 f = std::make_shared<DataAbort>( 861 currState->vaddr_tainted, 862 TlbEntry::DomainType::NoAccess, | 860 if (fault) { 861 Fault f; 862 if (currState->isFetch) 863 f = std::make_shared<PrefetchAbort>( 864 currState->vaddr_tainted, 865 ArmFault::TranslationLL + L0, isStage2, 866 ArmFault::LpaeTran); 867 else 868 f = std::make_shared<DataAbort>( 869 currState->vaddr_tainted, 870 TlbEntry::DomainType::NoAccess, |
863 currState->isWrite, | 871 is_atomic ? false : currState->isWrite, |
864 ArmFault::TranslationLL + L0, 865 isStage2, ArmFault::LpaeTran); 866 867 if (currState->timing) { 868 pending = false; 869 nextWalk(currState->tc); 870 currState = NULL; 871 } else { --- 69 unchanged lines hidden (view full) --- 941 currState->vaddr_tainted, 942 ArmFault::AddressSizeLL + start_lookup_level, 943 isStage2, 944 ArmFault::LpaeTran); 945 else 946 f = std::make_shared<DataAbort>( 947 currState->vaddr_tainted, 948 TlbEntry::DomainType::NoAccess, | 872 ArmFault::TranslationLL + L0, 873 isStage2, ArmFault::LpaeTran); 874 875 if (currState->timing) { 876 pending = false; 877 nextWalk(currState->tc); 878 currState = NULL; 879 } else { --- 69 unchanged lines hidden (view full) --- 949 currState->vaddr_tainted, 950 ArmFault::AddressSizeLL + start_lookup_level, 951 isStage2, 952 ArmFault::LpaeTran); 953 else 954 f = std::make_shared<DataAbort>( 955 currState->vaddr_tainted, 956 TlbEntry::DomainType::NoAccess, |
949 currState->isWrite, | 957 is_atomic ? false : currState->isWrite, |
950 ArmFault::AddressSizeLL + start_lookup_level, 951 isStage2, 952 ArmFault::LpaeTran); 953 954 955 if (currState->timing) { 956 pending = false; 957 nextWalk(currState->tc); --- 495 unchanged lines hidden (view full) --- 1453 1454 currState->l1Desc.data = htog(currState->l1Desc.data, 1455 byteOrder(currState->tc)); 1456 1457 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1458 currState->vaddr_tainted, currState->l1Desc.data); 1459 TlbEntry te; 1460 | 958 ArmFault::AddressSizeLL + start_lookup_level, 959 isStage2, 960 ArmFault::LpaeTran); 961 962 963 if (currState->timing) { 964 pending = false; 965 nextWalk(currState->tc); --- 495 unchanged lines hidden (view full) --- 1461 1462 currState->l1Desc.data = htog(currState->l1Desc.data, 1463 byteOrder(currState->tc)); 1464 1465 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 1466 currState->vaddr_tainted, currState->l1Desc.data); 1467 TlbEntry te; 1468 |
1469 const bool is_atomic = currState->req->isAtomic(); 1470 |
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1461 switch (currState->l1Desc.type()) { 1462 case L1Descriptor::Ignore: 1463 case L1Descriptor::Reserved: 1464 if (!currState->timing) { 1465 currState->tc = NULL; 1466 currState->req = NULL; 1467 } 1468 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); --- 4 unchanged lines hidden (view full) --- 1473 ArmFault::TranslationLL + L1, 1474 isStage2, 1475 ArmFault::VmsaTran); 1476 else 1477 currState->fault = 1478 std::make_shared<DataAbort>( 1479 currState->vaddr_tainted, 1480 TlbEntry::DomainType::NoAccess, | 1471 switch (currState->l1Desc.type()) { 1472 case L1Descriptor::Ignore: 1473 case L1Descriptor::Reserved: 1474 if (!currState->timing) { 1475 currState->tc = NULL; 1476 currState->req = NULL; 1477 } 1478 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); --- 4 unchanged lines hidden (view full) --- 1483 ArmFault::TranslationLL + L1, 1484 isStage2, 1485 ArmFault::VmsaTran); 1486 else 1487 currState->fault = 1488 std::make_shared<DataAbort>( 1489 currState->vaddr_tainted, 1490 TlbEntry::DomainType::NoAccess, |
1481 currState->isWrite, | 1491 is_atomic ? false : currState->isWrite, |
1482 ArmFault::TranslationLL + L1, isStage2, 1483 ArmFault::VmsaTran); 1484 return; 1485 case L1Descriptor::Section: 1486 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1487 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1488 * enabled if set, do l1.Desc.setAp0() instead of generating 1489 * AccessFlag0 1490 */ 1491 1492 currState->fault = std::make_shared<DataAbort>( 1493 currState->vaddr_tainted, 1494 currState->l1Desc.domain(), | 1492 ArmFault::TranslationLL + L1, isStage2, 1493 ArmFault::VmsaTran); 1494 return; 1495 case L1Descriptor::Section: 1496 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { 1497 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 1498 * enabled if set, do l1.Desc.setAp0() instead of generating 1499 * AccessFlag0 1500 */ 1501 1502 currState->fault = std::make_shared<DataAbort>( 1503 currState->vaddr_tainted, 1504 currState->l1Desc.domain(), |
1495 currState->isWrite, | 1505 is_atomic ? false : currState->isWrite, |
1496 ArmFault::AccessFlagLL + L1, 1497 isStage2, 1498 ArmFault::VmsaTran); 1499 } 1500 if (currState->l1Desc.supersection()) { 1501 panic("Haven't implemented supersections\n"); 1502 } 1503 insertTableEntry(currState->l1Desc, false); --- 46 unchanged lines hidden (view full) --- 1550 currState->vaddr_tainted, 1551 src + currState->longDesc.lookupLevel, 1552 isStage2, 1553 ArmFault::LpaeTran); 1554 } else { 1555 return std::make_shared<DataAbort>( 1556 currState->vaddr_tainted, 1557 TlbEntry::DomainType::NoAccess, | 1506 ArmFault::AccessFlagLL + L1, 1507 isStage2, 1508 ArmFault::VmsaTran); 1509 } 1510 if (currState->l1Desc.supersection()) { 1511 panic("Haven't implemented supersections\n"); 1512 } 1513 insertTableEntry(currState->l1Desc, false); --- 46 unchanged lines hidden (view full) --- 1560 currState->vaddr_tainted, 1561 src + currState->longDesc.lookupLevel, 1562 isStage2, 1563 ArmFault::LpaeTran); 1564 } else { 1565 return std::make_shared<DataAbort>( 1566 currState->vaddr_tainted, 1567 TlbEntry::DomainType::NoAccess, |
1558 currState->isWrite, | 1568 currState->req->isAtomic() ? false : currState->isWrite, |
1559 src + currState->longDesc.lookupLevel, 1560 isStage2, 1561 ArmFault::LpaeTran); 1562 } 1563} 1564 1565void 1566TableWalker::doLongDescriptor() --- 27 unchanged lines hidden (view full) --- 1594 currState->longDesc.data, 1595 currState->longDesc.type()); 1596 } 1597 1598 TlbEntry te; 1599 1600 switch (currState->longDesc.type()) { 1601 case LongDescriptor::Invalid: | 1569 src + currState->longDesc.lookupLevel, 1570 isStage2, 1571 ArmFault::LpaeTran); 1572 } 1573} 1574 1575void 1576TableWalker::doLongDescriptor() --- 27 unchanged lines hidden (view full) --- 1604 currState->longDesc.data, 1605 currState->longDesc.type()); 1606 } 1607 1608 TlbEntry te; 1609 1610 switch (currState->longDesc.type()) { 1611 case LongDescriptor::Invalid: |
1602 if (!currState->timing) { 1603 currState->tc = NULL; 1604 currState->req = NULL; 1605 } 1606 | |
1607 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1608 currState->longDesc.lookupLevel, 1609 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1610 1611 currState->fault = generateLongDescFault(ArmFault::TranslationLL); | 1612 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n", 1613 currState->longDesc.lookupLevel, 1614 ArmFault::TranslationLL + currState->longDesc.lookupLevel); 1615 1616 currState->fault = generateLongDescFault(ArmFault::TranslationLL); |
1617 if (!currState->timing) { 1618 currState->tc = NULL; 1619 currState->req = NULL; 1620 } |
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1612 return; 1613 1614 case LongDescriptor::Block: 1615 case LongDescriptor::Page: 1616 { 1617 auto fault_source = ArmFault::FaultSourceInvalid; 1618 // Check for address size fault 1619 if (checkAddrSizeFaultAArch64( --- 110 unchanged lines hidden (view full) --- 1730 1731 currState->l2Desc.data = htog(currState->l2Desc.data, 1732 byteOrder(currState->tc)); 1733 1734 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1735 currState->vaddr_tainted, currState->l2Desc.data); 1736 TlbEntry te; 1737 | 1621 return; 1622 1623 case LongDescriptor::Block: 1624 case LongDescriptor::Page: 1625 { 1626 auto fault_source = ArmFault::FaultSourceInvalid; 1627 // Check for address size fault 1628 if (checkAddrSizeFaultAArch64( --- 110 unchanged lines hidden (view full) --- 1739 1740 currState->l2Desc.data = htog(currState->l2Desc.data, 1741 byteOrder(currState->tc)); 1742 1743 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 1744 currState->vaddr_tainted, currState->l2Desc.data); 1745 TlbEntry te; 1746 |
1747 const bool is_atomic = currState->req->isAtomic(); 1748 |
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1738 if (currState->l2Desc.invalid()) { 1739 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1740 if (!currState->timing) { 1741 currState->tc = NULL; 1742 currState->req = NULL; 1743 } 1744 if (currState->isFetch) 1745 currState->fault = std::make_shared<PrefetchAbort>( 1746 currState->vaddr_tainted, 1747 ArmFault::TranslationLL + L2, 1748 isStage2, 1749 ArmFault::VmsaTran); 1750 else 1751 currState->fault = std::make_shared<DataAbort>( 1752 currState->vaddr_tainted, currState->l1Desc.domain(), | 1749 if (currState->l2Desc.invalid()) { 1750 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); 1751 if (!currState->timing) { 1752 currState->tc = NULL; 1753 currState->req = NULL; 1754 } 1755 if (currState->isFetch) 1756 currState->fault = std::make_shared<PrefetchAbort>( 1757 currState->vaddr_tainted, 1758 ArmFault::TranslationLL + L2, 1759 isStage2, 1760 ArmFault::VmsaTran); 1761 else 1762 currState->fault = std::make_shared<DataAbort>( 1763 currState->vaddr_tainted, currState->l1Desc.domain(), |
1753 currState->isWrite, ArmFault::TranslationLL + L2, | 1764 is_atomic ? false : currState->isWrite, 1765 ArmFault::TranslationLL + L2, |
1754 isStage2, 1755 ArmFault::VmsaTran); 1756 return; 1757 } 1758 1759 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1760 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1761 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1762 */ 1763 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1764 currState->sctlr.afe, currState->l2Desc.ap()); 1765 1766 currState->fault = std::make_shared<DataAbort>( 1767 currState->vaddr_tainted, | 1766 isStage2, 1767 ArmFault::VmsaTran); 1768 return; 1769 } 1770 1771 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { 1772 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 1773 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 1774 */ 1775 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n", 1776 currState->sctlr.afe, currState->l2Desc.ap()); 1777 1778 currState->fault = std::make_shared<DataAbort>( 1779 currState->vaddr_tainted, |
1768 TlbEntry::DomainType::NoAccess, currState->isWrite, | 1780 TlbEntry::DomainType::NoAccess, 1781 is_atomic ? false : currState->isWrite, |
1769 ArmFault::AccessFlagLL + L2, isStage2, 1770 ArmFault::VmsaTran); 1771 } 1772 1773 insertTableEntry(currState->l2Desc, false); 1774} 1775 1776void --- 505 unchanged lines hidden --- | 1782 ArmFault::AccessFlagLL + L2, isStage2, 1783 ArmFault::VmsaTran); 1784 } 1785 1786 insertTableEntry(currState->l2Desc, false); 1787} 1788 1789void --- 505 unchanged lines hidden --- |