table_walker.cc (12709:faf5b471d5ce) | table_walker.cc (12735:e3da526a0654) |
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1/* 2 * Copyright (c) 2010, 2012-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 216 unchanged lines hidden (view full) --- 225 } 226 pendingChange(); 227 228 currState->startTime = curTick(); 229 currState->tc = _tc; 230 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 231 // aarch32/translation/translation/AArch32.TranslateAddress dictates 232 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. | 1/* 2 * Copyright (c) 2010, 2012-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 216 unchanged lines hidden (view full) --- 225 } 226 pendingChange(); 227 228 currState->startTime = curTick(); 229 currState->tc = _tc; 230 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 231 // aarch32/translation/translation/AArch32.TranslateAddress dictates 232 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. |
233 currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || 234 ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); 235 currState->el = currEL(_tc); | 233 if (isStage2) { 234 currState->el = EL1; 235 currState->aarch64 = ELIs64(_tc, EL2); 236 } else { 237 currState->el = 238 TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); 239 currState->aarch64 = 240 ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); 241 } |
236 currState->transState = _trans; 237 currState->req = _req; 238 currState->fault = NoFault; 239 currState->asid = _asid; 240 currState->vmid = _vmid; 241 currState->isHyp = _isHyp; 242 currState->timing = _timing; 243 currState->functional = _functional; --- 114 unchanged lines hidden (view full) --- 358void 359TableWalker::processWalkWrapper() 360{ 361 assert(!currState); 362 assert(pendingQueue.size()); 363 pendingChange(); 364 currState = pendingQueue.front(); 365 | 242 currState->transState = _trans; 243 currState->req = _req; 244 currState->fault = NoFault; 245 currState->asid = _asid; 246 currState->vmid = _vmid; 247 currState->isHyp = _isHyp; 248 currState->timing = _timing; 249 currState->functional = _functional; --- 114 unchanged lines hidden (view full) --- 364void 365TableWalker::processWalkWrapper() 366{ 367 assert(!currState); 368 assert(pendingQueue.size()); 369 pendingChange(); 370 currState = pendingQueue.front(); 371 |
366 ExceptionLevel target_el = EL0; 367 if (currState->aarch64) 368 target_el = currEL(currState->tc); 369 else 370 target_el = EL1; 371 | |
372 // Check if a previous walk filled this request already 373 // @TODO Should this always be the TLB or should we look in the stage2 TLB? 374 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 375 currState->vmid, currState->isHyp, currState->isSecure, true, false, | 372 // Check if a previous walk filled this request already 373 // @TODO Should this always be the TLB or should we look in the stage2 TLB? 374 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 375 currState->vmid, currState->isHyp, currState->isSecure, true, false, |
376 target_el); | 376 currState->el); |
377 378 // Check if we still need to have a walk for this request. If the requesting 379 // instruction has been squashed, or a previous walk has filled the TLB with 380 // a match, we just want to get rid of the walk. The latter could happen 381 // when there are multiple outstanding misses to a single page and a 382 // previous request has been successfully translated. 383 if (!currState->transState->squashed() && !te) { 384 // We've got a valid request, lets process it --- 49 unchanged lines hidden (view full) --- 434 // delete the current request 435 delete currState; 436 437 // peak at the next one 438 if (pendingQueue.size()) { 439 currState = pendingQueue.front(); 440 te = tlb->lookup(currState->vaddr, currState->asid, 441 currState->vmid, currState->isHyp, currState->isSecure, true, | 377 378 // Check if we still need to have a walk for this request. If the requesting 379 // instruction has been squashed, or a previous walk has filled the TLB with 380 // a match, we just want to get rid of the walk. The latter could happen 381 // when there are multiple outstanding misses to a single page and a 382 // previous request has been successfully translated. 383 if (!currState->transState->squashed() && !te) { 384 // We've got a valid request, lets process it --- 49 unchanged lines hidden (view full) --- 434 // delete the current request 435 delete currState; 436 437 // peak at the next one 438 if (pendingQueue.size()) { 439 currState = pendingQueue.front(); 440 te = tlb->lookup(currState->vaddr, currState->asid, 441 currState->vmid, currState->isHyp, currState->isSecure, true, |
442 false, target_el); | 442 false, currState->el); |
443 } else { 444 // Terminate the loop, nothing more to do 445 currState = NULL; 446 } 447 } 448 pendingChange(); 449 450 // if we still have pending translations, schedule more work --- 1847 unchanged lines hidden --- | 443 } else { 444 // Terminate the loop, nothing more to do 445 currState = NULL; 446 } 447 } 448 pendingChange(); 449 450 // if we still have pending translations, schedule more work --- 1847 unchanged lines hidden --- |