1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 * Giacomo Gabrielli
39 */
40#include "arch/arm/table_walker.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/stage2_mmu.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "cpu/base.hh"
49#include "cpu/thread_context.hh"
50#include "debug/Checkpoint.hh"
51#include "debug/Drain.hh"
52#include "debug/TLB.hh"
53#include "debug/TLBVerbose.hh"
54#include "dev/dma_device.hh"
55#include "sim/system.hh"
56
57using namespace ArmISA;
58
59TableWalker::TableWalker(const Params *p)
60 : MemObject(p),
61 stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
62 isStage2(p->is_stage2), tlb(NULL),
63 currState(NULL), pending(false),
64 numSquashable(p->num_squash_per_cycle),
65 pendingReqs(0),
66 pendingChangeTick(curTick()),
67 doL1DescEvent(this), doL2DescEvent(this),
68 doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this),
69 doL3LongDescEvent(this),
70 doProcessEvent(this)
71{
72 sctlr = 0;
73
74 // Cache system-level properties
75 if (FullSystem) {
76 ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys);
77 assert(armSys);
78 haveSecurity = armSys->haveSecurity();
79 _haveLPAE = armSys->haveLPAE();
80 _haveVirtualization = armSys->haveVirtualization();
81 physAddrRange = armSys->physAddrRange();
82 _haveLargeAsid64 = armSys->haveLargeAsid64();
83 } else {
84 haveSecurity = _haveLPAE = _haveVirtualization = false;
85 _haveLargeAsid64 = false;
86 physAddrRange = 32;
87 }
88
89}
90
91TableWalker::~TableWalker()
92{
93 ;
94}
95
96void
97TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
98{
99 stage2Mmu = m;
100 port = &m->getPort();
101 masterId = master_id;
102}
103
104void
105TableWalker::init()
106{
107 fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n");
108 fatal_if(!port, "Table walker must have a valid port\n");
109 fatal_if(!tlb, "Table walker must have a valid TLB\n");
110}
111
112BaseMasterPort&
113TableWalker::getMasterPort(const std::string &if_name, PortID idx)
114{
115 if (if_name == "port") {
116 if (!isStage2) {
117 return *port;
118 } else {
119 fatal("Cannot access table walker port through stage-two walker\n");
120 }
121 }
122 return MemObject::getMasterPort(if_name, idx);
123}
124
125TableWalker::WalkerState::WalkerState() :
126 tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
127 asid(0), vmid(0), isHyp(false), transState(nullptr),
128 vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false),
129 secureLookup(false), rwTable(false), userTable(false), xnTable(false),
130 pxnTable(false), stage2Req(false), doingStage2(false),
131 stage2Tran(nullptr), timing(false), functional(false),
132 mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
133 delayed(false), tableWalker(nullptr)
134{
135}
136
137void
138TableWalker::completeDrain()
139{
140 if (drainState() == DrainState::Draining &&
141 stateQueues[L1].empty() && stateQueues[L2].empty() &&
142 pendingQueue.empty()) {
143
144 DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
145 signalDrainDone();
146 }
147}
148
149DrainState
150TableWalker::drain()
151{
152 bool state_queues_not_empty = false;
153
154 for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) {
155 if (!stateQueues[i].empty()) {
156 state_queues_not_empty = true;
157 break;
158 }
159 }
160
161 if (state_queues_not_empty || pendingQueue.size()) {
162 DPRINTF(Drain, "TableWalker not drained\n");
163 return DrainState::Draining;
164 } else {
165 DPRINTF(Drain, "TableWalker free, no need to drain\n");
166 return DrainState::Drained;
167 }
168}
169
170void
171TableWalker::drainResume()
172{
173 if (params()->sys->isTimingMode() && currState) {
174 delete currState;
175 currState = NULL;
176 pendingChange();
177 }
178}
179
180Fault
181TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
182 uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
183 TLB::Translation *_trans, bool _timing, bool _functional,
184 bool secure, TLB::ArmTranslationType tranType)
185{
186 assert(!(_functional && _timing));
187 ++statWalks;
188
189 WalkerState *savedCurrState = NULL;
190
191 if (!currState && !_functional) {
192 // For atomic mode, a new WalkerState instance should be only created
193 // once per TLB. For timing mode, a new instance is generated for every
194 // TLB miss.
195 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n");
196
197 currState = new WalkerState();
198 currState->tableWalker = this;
199 } else if (_functional) {
200 // If we are mixing functional mode with timing (or even
201 // atomic), we need to to be careful and clean up after
202 // ourselves to not risk getting into an inconsistent state.
203 DPRINTF(TLBVerbose, "creating functional instance of WalkerState\n");
204 savedCurrState = currState;
205 currState = new WalkerState();
206 currState->tableWalker = this;
207 } else if (_timing) {
208 // This is a translation that was completed and then faulted again
209 // because some underlying parameters that affect the translation
210 // changed out from under us (e.g. asid). It will either be a
211 // misprediction, in which case nothing will happen or we'll use
212 // this fault to re-execute the faulting instruction which should clean
213 // up everything.
214 if (currState->vaddr_tainted == _req->getVaddr()) {
215 ++statSquashedBefore;
216 return std::make_shared<ReExec>();
217 }
218 }
219 pendingChange();
220
221 currState->startTime = curTick();
222 currState->tc = _tc;
223 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
224 // aarch32/translation/translation/AArch32.TranslateAddress dictates
225 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
226 currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) ||
227 ((currEL(_tc) == EL0) && ELIs64(_tc, EL1));
228 currState->el = currEL(_tc);
229 currState->transState = _trans;
230 currState->req = _req;
231 currState->fault = NoFault;
232 currState->asid = _asid;
233 currState->vmid = _vmid;
234 currState->isHyp = _isHyp;
235 currState->timing = _timing;
236 currState->functional = _functional;
237 currState->mode = _mode;
238 currState->tranType = tranType;
239 currState->isSecure = secure;
240 currState->physAddrRange = physAddrRange;
241
242 /** @todo These should be cached or grabbed from cached copies in
243 the TLB, all these miscreg reads are expensive */
244 currState->vaddr_tainted = currState->req->getVaddr();
245 if (currState->aarch64)
246 currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted,
247 currState->tc, currState->el);
248 else
249 currState->vaddr = currState->vaddr_tainted;
250
251 if (currState->aarch64) {
252 if (isStage2) {
253 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
254 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
255 } else switch (currState->el) {
256 case EL0:
257 case EL1:
258 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
259 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
260 break;
261 case EL2:
262 assert(_haveVirtualization);
263 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
264 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
265 break;
266 case EL3:
267 assert(haveSecurity);
268 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
269 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
270 break;
271 default:
272 panic("Invalid exception level");
273 break;
274 }
275 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
276 } else {
277 currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
278 MISCREG_SCTLR, currState->tc, !currState->isSecure));
279 currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
280 MISCREG_TTBCR, currState->tc, !currState->isSecure));
281 currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR);
282 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR);
283 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR);
284 }
285 sctlr = currState->sctlr;
286
287 currState->isFetch = (currState->mode == TLB::Execute);
288 currState->isWrite = (currState->mode == TLB::Write);
289
290 statRequestOrigin[REQUESTED][currState->isFetch]++;
291
292 // We only do a second stage of translation if we're not secure, or in
293 // hyp mode, the second stage MMU is enabled, and this table walker
294 // instance is the first stage.
295 currState->doingStage2 = false;
296 currState->stage2Req = currState->hcr.vm && !isStage2 &&
297 !currState->isSecure && !currState->isHyp;
298
299 bool long_desc_format = currState->aarch64 || _isHyp || isStage2 ||
300 longDescFormatInUse(currState->tc);
301
302 if (long_desc_format) {
303 // Helper variables used for hierarchical permissions
304 currState->secureLookup = currState->isSecure;
305 currState->rwTable = true;
306 currState->userTable = true;
307 currState->xnTable = false;
308 currState->pxnTable = false;
309
310 ++statWalksLongDescriptor;
311 } else {
312 ++statWalksShortDescriptor;
313 }
314
315 if (!currState->timing) {
316 Fault fault = NoFault;
317 if (currState->aarch64)
318 fault = processWalkAArch64();
319 else if (long_desc_format)
320 fault = processWalkLPAE();
321 else
322 fault = processWalk();
323
324 // If this was a functional non-timing access restore state to
325 // how we found it.
326 if (currState->functional) {
327 delete currState;
328 currState = savedCurrState;
329 }
330 return fault;
331 }
332
333 if (pending || pendingQueue.size()) {
334 pendingQueue.push_back(currState);
335 currState = NULL;
336 pendingChange();
337 } else {
338 pending = true;
339 pendingChange();
340 if (currState->aarch64)
341 return processWalkAArch64();
342 else if (long_desc_format)
343 return processWalkLPAE();
344 else
345 return processWalk();
346 }
347
348 return NoFault;
349}
350
351void
352TableWalker::processWalkWrapper()
353{
354 assert(!currState);
355 assert(pendingQueue.size());
356 pendingChange();
357 currState = pendingQueue.front();
358
359 ExceptionLevel target_el = EL0;
360 if (currState->aarch64)
361 target_el = currEL(currState->tc);
362 else
363 target_el = EL1;
364
365 // Check if a previous walk filled this request already
366 // @TODO Should this always be the TLB or should we look in the stage2 TLB?
367 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
368 currState->vmid, currState->isHyp, currState->isSecure, true, false,
369 target_el);
370
371 // Check if we still need to have a walk for this request. If the requesting
372 // instruction has been squashed, or a previous walk has filled the TLB with
373 // a match, we just want to get rid of the walk. The latter could happen
374 // when there are multiple outstanding misses to a single page and a
375 // previous request has been successfully translated.
376 if (!currState->transState->squashed() && !te) {
377 // We've got a valid request, lets process it
378 pending = true;
379 pendingQueue.pop_front();
380 // Keep currState in case one of the processWalk... calls NULLs it
381 WalkerState *curr_state_copy = currState;
382 Fault f;
383 if (currState->aarch64)
384 f = processWalkAArch64();
385 else if (longDescFormatInUse(currState->tc) ||
386 currState->isHyp || isStage2)
387 f = processWalkLPAE();
388 else
389 f = processWalk();
390
391 if (f != NoFault) {
392 curr_state_copy->transState->finish(f, curr_state_copy->req,
393 curr_state_copy->tc, curr_state_copy->mode);
394
395 delete curr_state_copy;
396 }
397 return;
398 }
399
400
401 // If the instruction that we were translating for has been
402 // squashed we shouldn't bother.
403 unsigned num_squashed = 0;
404 ThreadContext *tc = currState->tc;
405 while ((num_squashed < numSquashable) && currState &&
406 (currState->transState->squashed() || te)) {
407 pendingQueue.pop_front();
408 num_squashed++;
409 statSquashedBefore++;
410
411 DPRINTF(TLB, "Squashing table walk for address %#x\n",
412 currState->vaddr_tainted);
413
414 if (currState->transState->squashed()) {
415 // finish the translation which will delete the translation object
416 currState->transState->finish(
417 std::make_shared<UnimpFault>("Squashed Inst"),
418 currState->req, currState->tc, currState->mode);
419 } else {
420 // translate the request now that we know it will work
421 statWalkServiceTime.sample(curTick() - currState->startTime);
422 tlb->translateTiming(currState->req, currState->tc,
423 currState->transState, currState->mode);
424
425 }
426
427 // delete the current request
428 delete currState;
429
430 // peak at the next one
431 if (pendingQueue.size()) {
432 currState = pendingQueue.front();
433 te = tlb->lookup(currState->vaddr, currState->asid,
434 currState->vmid, currState->isHyp, currState->isSecure, true,
435 false, target_el);
436 } else {
437 // Terminate the loop, nothing more to do
438 currState = NULL;
439 }
440 }
441 pendingChange();
442
443 // if we still have pending translations, schedule more work
444 nextWalk(tc);
445 currState = NULL;
446}
447
448Fault
449TableWalker::processWalk()
450{
451 Addr ttbr = 0;
452
453 // If translation isn't enabled, we shouldn't be here
454 assert(currState->sctlr.m || isStage2);
455
456 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
457 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31,
458 32 - currState->ttbcr.n));
459
460 statWalkWaitTime.sample(curTick() - currState->startTime);
461
462 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31,
463 32 - currState->ttbcr.n)) {
464 DPRINTF(TLB, " - Selecting TTBR0\n");
465 // Check if table walk is allowed when Security Extensions are enabled
466 if (haveSecurity && currState->ttbcr.pd0) {
467 if (currState->isFetch)
468 return std::make_shared<PrefetchAbort>(
469 currState->vaddr_tainted,
470 ArmFault::TranslationLL + L1,
471 isStage2,
472 ArmFault::VmsaTran);
473 else
474 return std::make_shared<DataAbort>(
475 currState->vaddr_tainted,
476 TlbEntry::DomainType::NoAccess, currState->isWrite,
477 ArmFault::TranslationLL + L1, isStage2,
478 ArmFault::VmsaTran);
479 }
480 ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
481 MISCREG_TTBR0, currState->tc, !currState->isSecure));
482 } else {
483 DPRINTF(TLB, " - Selecting TTBR1\n");
484 // Check if table walk is allowed when Security Extensions are enabled
485 if (haveSecurity && currState->ttbcr.pd1) {
486 if (currState->isFetch)
487 return std::make_shared<PrefetchAbort>(
488 currState->vaddr_tainted,
489 ArmFault::TranslationLL + L1,
490 isStage2,
491 ArmFault::VmsaTran);
492 else
493 return std::make_shared<DataAbort>(
494 currState->vaddr_tainted,
495 TlbEntry::DomainType::NoAccess, currState->isWrite,
496 ArmFault::TranslationLL + L1, isStage2,
497 ArmFault::VmsaTran);
498 }
499 ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
500 MISCREG_TTBR1, currState->tc, !currState->isSecure));
501 currState->ttbcr.n = 0;
502 }
503
504 Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) |
505 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
506 DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr,
507 currState->isSecure ? "s" : "ns");
508
509 // Trickbox address check
510 Fault f;
511 f = testWalk(l1desc_addr, sizeof(uint32_t),
512 TlbEntry::DomainType::NoAccess, L1);
513 if (f) {
514 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
515 if (currState->timing) {
516 pending = false;
517 nextWalk(currState->tc);
518 currState = NULL;
519 } else {
520 currState->tc = NULL;
521 currState->req = NULL;
522 }
523 return f;
524 }
525
526 Request::Flags flag = Request::PT_WALK;
527 if (currState->sctlr.c == 0) {
528 flag.set(Request::UNCACHEABLE);
529 }
530
531 if (currState->isSecure) {
532 flag.set(Request::SECURE);
533 }
534
535 bool delayed;
536 delayed = fetchDescriptor(l1desc_addr, (uint8_t*)&currState->l1Desc.data,
537 sizeof(uint32_t), flag, L1, &doL1DescEvent,
538 &TableWalker::doL1Descriptor);
539 if (!delayed) {
540 f = currState->fault;
541 }
542
543 return f;
544}
545
546Fault
547TableWalker::processWalkLPAE()
548{
549 Addr ttbr, ttbr0_max, ttbr1_min, desc_addr;
550 int tsz, n;
551 LookupLevel start_lookup_level = L1;
552
553 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n",
554 currState->vaddr_tainted, currState->ttbcr);
555
556 statWalkWaitTime.sample(curTick() - currState->startTime);
557
558 Request::Flags flag = Request::PT_WALK;
559 if (currState->isSecure)
560 flag.set(Request::SECURE);
561
562 // work out which base address register to use, if in hyp mode we always
563 // use HTTBR
564 if (isStage2) {
565 DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n");
566 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR);
567 tsz = sext<4>(currState->vtcr.t0sz);
568 start_lookup_level = currState->vtcr.sl0 ? L1 : L2;
569 } else if (currState->isHyp) {
570 DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n");
571 ttbr = currState->tc->readMiscReg(MISCREG_HTTBR);
572 tsz = currState->htcr.t0sz;
573 } else {
574 assert(longDescFormatInUse(currState->tc));
575
576 // Determine boundaries of TTBR0/1 regions
577 if (currState->ttbcr.t0sz)
578 ttbr0_max = (1ULL << (32 - currState->ttbcr.t0sz)) - 1;
579 else if (currState->ttbcr.t1sz)
580 ttbr0_max = (1ULL << 32) -
581 (1ULL << (32 - currState->ttbcr.t1sz)) - 1;
582 else
583 ttbr0_max = (1ULL << 32) - 1;
584 if (currState->ttbcr.t1sz)
585 ttbr1_min = (1ULL << 32) - (1ULL << (32 - currState->ttbcr.t1sz));
586 else
587 ttbr1_min = (1ULL << (32 - currState->ttbcr.t0sz));
588
589 // The following code snippet selects the appropriate translation table base
590 // address (TTBR0 or TTBR1) and the appropriate starting lookup level
591 // depending on the address range supported by the translation table (ARM
592 // ARM issue C B3.6.4)
593 if (currState->vaddr <= ttbr0_max) {
594 DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n");
595 // Check if table walk is allowed
596 if (currState->ttbcr.epd0) {
597 if (currState->isFetch)
598 return std::make_shared<PrefetchAbort>(
599 currState->vaddr_tainted,
600 ArmFault::TranslationLL + L1,
601 isStage2,
602 ArmFault::LpaeTran);
603 else
604 return std::make_shared<DataAbort>(
605 currState->vaddr_tainted,
606 TlbEntry::DomainType::NoAccess,
607 currState->isWrite,
608 ArmFault::TranslationLL + L1,
609 isStage2,
610 ArmFault::LpaeTran);
611 }
612 ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
613 MISCREG_TTBR0, currState->tc, !currState->isSecure));
614 tsz = currState->ttbcr.t0sz;
615 if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB
616 start_lookup_level = L2;
617 } else if (currState->vaddr >= ttbr1_min) {
618 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
619 // Check if table walk is allowed
620 if (currState->ttbcr.epd1) {
621 if (currState->isFetch)
622 return std::make_shared<PrefetchAbort>(
623 currState->vaddr_tainted,
624 ArmFault::TranslationLL + L1,
625 isStage2,
626 ArmFault::LpaeTran);
627 else
628 return std::make_shared<DataAbort>(
629 currState->vaddr_tainted,
630 TlbEntry::DomainType::NoAccess,
631 currState->isWrite,
632 ArmFault::TranslationLL + L1,
633 isStage2,
634 ArmFault::LpaeTran);
635 }
636 ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
637 MISCREG_TTBR1, currState->tc, !currState->isSecure));
638 tsz = currState->ttbcr.t1sz;
639 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB
640 start_lookup_level = L2;
641 } else {
642 // Out of boundaries -> translation fault
643 if (currState->isFetch)
644 return std::make_shared<PrefetchAbort>(
645 currState->vaddr_tainted,
646 ArmFault::TranslationLL + L1,
647 isStage2,
648 ArmFault::LpaeTran);
649 else
650 return std::make_shared<DataAbort>(
651 currState->vaddr_tainted,
652 TlbEntry::DomainType::NoAccess,
653 currState->isWrite, ArmFault::TranslationLL + L1,
654 isStage2, ArmFault::LpaeTran);
655 }
656
657 }
658
659 // Perform lookup (ARM ARM issue C B3.6.6)
660 if (start_lookup_level == L1) {
661 n = 5 - tsz;
662 desc_addr = mbits(ttbr, 39, n) |
663 (bits(currState->vaddr, n + 26, 30) << 3);
664 DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n",
665 desc_addr, currState->isSecure ? "s" : "ns");
666 } else {
667 // Skip first-level lookup
668 n = (tsz >= 2 ? 14 - tsz : 12);
669 desc_addr = mbits(ttbr, 39, n) |
670 (bits(currState->vaddr, n + 17, 21) << 3);
671 DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n",
672 desc_addr, currState->isSecure ? "s" : "ns");
673 }
674
675 // Trickbox address check
676 Fault f = testWalk(desc_addr, sizeof(uint64_t),
677 TlbEntry::DomainType::NoAccess, start_lookup_level);
678 if (f) {
679 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
680 if (currState->timing) {
681 pending = false;
682 nextWalk(currState->tc);
683 currState = NULL;
684 } else {
685 currState->tc = NULL;
686 currState->req = NULL;
687 }
688 return f;
689 }
690
691 if (currState->sctlr.c == 0) {
692 flag.set(Request::UNCACHEABLE);
693 }
694
695 currState->longDesc.lookupLevel = start_lookup_level;
696 currState->longDesc.aarch64 = false;
697 currState->longDesc.grainSize = Grain4KB;
698
699 Event *event = start_lookup_level == L1 ? (Event *) &doL1LongDescEvent
700 : (Event *) &doL2LongDescEvent;
701
702 bool delayed = fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
703 sizeof(uint64_t), flag, start_lookup_level,
704 event, &TableWalker::doLongDescriptor);
705 if (!delayed) {
706 f = currState->fault;
707 }
708
709 return f;
710}
711
712unsigned
713TableWalker::adjustTableSizeAArch64(unsigned tsz)
714{
715 if (tsz < 25)
716 return 25;
717 if (tsz > 48)
718 return 48;
719 return tsz;
720}
721
722bool
723TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange)
724{
725 return (currPhysAddrRange != MaxPhysAddrRange &&
726 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange));
727}
728
729Fault
730TableWalker::processWalkAArch64()
731{
732 assert(currState->aarch64);
733
734 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
735 currState->vaddr_tainted, currState->tcr);
736
737 static const GrainSize GrainMapDefault[] =
738 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
739 static const GrainSize GrainMap_EL1_tg1[] =
740 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };
741
742 statWalkWaitTime.sample(curTick() - currState->startTime);
743
744 // Determine TTBR, table size, granule size and phys. address range
745 Addr ttbr = 0;
746 int tsz = 0, ps = 0;
747 GrainSize tg = Grain4KB; // grain size computed from tg* field
748 bool fault = false;
749
750 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
751
752 switch (currState->el) {
753 case EL0:
754 case EL1:
755 if (isStage2) {
756 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
757 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
758 tsz = 64 - currState->vtcr.t0sz64;
759 tg = GrainMapDefault[currState->vtcr.tg0];
760 // ARM DDI 0487A.f D7-2148
761 // The starting level of stage 2 translation depends on
762 // VTCR_EL2.SL0 and VTCR_EL2.TG0
763 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
764 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
765 static const LookupLevel SLL[] = {
766 L2, L3, L3, __, // sl0 == 0
767 L1, L2, L2, __, // sl0 == 1, etc.
768 L0, L1, L1, __,
769 __, __, __, __
770 };
771 start_lookup_level = SLL[sl_tg];
772 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
773 "Cannot discern lookup level from vtcr.{sl0,tg0}");
774 } else switch (bits(currState->vaddr, 63,48)) {
775 case 0:
776 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
777 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
778 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
779 tg = GrainMapDefault[currState->tcr.tg0];
780 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
781 currState->tcr.epd0)
782 fault = true;
783 break;
784 case 0xffff:
785 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
786 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
787 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
788 tg = GrainMap_EL1_tg1[currState->tcr.tg1];
789 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
790 currState->tcr.epd1)
791 fault = true;
792 break;
793 default:
794 // top two bytes must be all 0s or all 1s, else invalid addr
795 fault = true;
796 }
797 ps = currState->tcr.ips;
798 break;
799 case EL2:
800 case EL3:
801 switch(bits(currState->vaddr, 63,48)) {
802 case 0:
803 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
804 if (currState->el == EL2)
805 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
806 else
807 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
808 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
809 tg = GrainMapDefault[currState->tcr.tg0];
810 break;
811 default:
812 // invalid addr if top two bytes are not all 0s
813 fault = true;
814 }
815 ps = currState->tcr.ips;
816 break;
817 }
818
819 if (fault) {
820 Fault f;
821 if (currState->isFetch)
822 f = std::make_shared<PrefetchAbort>(
823 currState->vaddr_tainted,
824 ArmFault::TranslationLL + L0, isStage2,
825 ArmFault::LpaeTran);
826 else
827 f = std::make_shared<DataAbort>(
828 currState->vaddr_tainted,
829 TlbEntry::DomainType::NoAccess,
830 currState->isWrite,
831 ArmFault::TranslationLL + L0,
832 isStage2, ArmFault::LpaeTran);
833
834 if (currState->timing) {
835 pending = false;
836 nextWalk(currState->tc);
837 currState = NULL;
838 } else {
839 currState->tc = NULL;
840 currState->req = NULL;
841 }
842 return f;
843
844 }
845
846 if (tg == ReservedGrain) {
847 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION "
848 "DEFINED behavior takes this to mean 4KB granules\n");
849 tg = Grain4KB;
850 }
851
852 // Determine starting lookup level
853 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library
854 // in ARM DDI 0487A. These table values correspond to the cascading tests
855 // to compute the lookup level and are of the form
856 // (grain_size + N*stride), for N = {1, 2, 3}.
857 // A value of 64 will never succeed and a value of 0 will always succeed.
858 if (start_lookup_level == MAX_LOOKUP_LEVELS) {
859 struct GrainMap {
860 GrainSize grain_size;
861 unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS];
862 };
863 static const GrainMap GM[] = {
864 { Grain4KB, { 39, 30, 0, 0 } },
865 { Grain16KB, { 47, 36, 25, 0 } },
866 { Grain64KB, { 64, 42, 29, 0 } }
867 };
868
869 const unsigned *lookup = NULL; // points to a lookup_level_cutoff
870
871 for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[]
872 if (tg == GM[i].grain_size) {
873 lookup = GM[i].lookup_level_cutoff;
874 break;
875 }
876 }
877 assert(lookup);
878
879 for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) {
880 if (tsz > lookup[L]) {
881 start_lookup_level = (LookupLevel) L;
882 break;
883 }
884 }
885 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
886 "Table walker couldn't find lookup level\n");
887 }
888
889 int stride = tg - 3;
890
891 // Determine table base address
892 int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg;
893 Addr base_addr = mbits(ttbr, 47, base_addr_lo);
894
895 // Determine physical address size and raise an Address Size Fault if
896 // necessary
897 int pa_range = decodePhysAddrRange64(ps);
898 // Clamp to lower limit
899 if (pa_range > physAddrRange)
900 currState->physAddrRange = physAddrRange;
901 else
902 currState->physAddrRange = pa_range;
903 if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) {
904 DPRINTF(TLB, "Address size fault before any lookup\n");
905 Fault f;
906 if (currState->isFetch)
907 f = std::make_shared<PrefetchAbort>(
908 currState->vaddr_tainted,
909 ArmFault::AddressSizeLL + start_lookup_level,
910 isStage2,
911 ArmFault::LpaeTran);
912 else
913 f = std::make_shared<DataAbort>(
914 currState->vaddr_tainted,
915 TlbEntry::DomainType::NoAccess,
916 currState->isWrite,
917 ArmFault::AddressSizeLL + start_lookup_level,
918 isStage2,
919 ArmFault::LpaeTran);
920
921
922 if (currState->timing) {
923 pending = false;
924 nextWalk(currState->tc);
925 currState = NULL;
926 } else {
927 currState->tc = NULL;
928 currState->req = NULL;
929 }
930 return f;
931
932 }
933
934 // Determine descriptor address
935 Addr desc_addr = base_addr |
936 (bits(currState->vaddr, tsz - 1,
937 stride * (3 - start_lookup_level) + tg) << 3);
938
939 // Trickbox address check
940 Fault f = testWalk(desc_addr, sizeof(uint64_t),
941 TlbEntry::DomainType::NoAccess, start_lookup_level);
942 if (f) {
943 DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
944 if (currState->timing) {
945 pending = false;
946 nextWalk(currState->tc);
947 currState = NULL;
948 } else {
949 currState->tc = NULL;
950 currState->req = NULL;
951 }
952 return f;
953 }
954
955 Request::Flags flag = Request::PT_WALK;
956 if (currState->sctlr.c == 0) {
957 flag.set(Request::UNCACHEABLE);
958 }
959
960 if (currState->isSecure) {
961 flag.set(Request::SECURE);
962 }
963
964 currState->longDesc.lookupLevel = start_lookup_level;
965 currState->longDesc.aarch64 = true;
966 currState->longDesc.grainSize = tg;
967
968 if (currState->timing) {
969 Event *event;
970 switch (start_lookup_level) {
971 case L0:
972 event = (Event *) &doL0LongDescEvent;
973 break;
974 case L1:
975 event = (Event *) &doL1LongDescEvent;
976 break;
977 case L2:
978 event = (Event *) &doL2LongDescEvent;
979 break;
980 case L3:
981 event = (Event *) &doL3LongDescEvent;
982 break;
983 default:
984 panic("Invalid table lookup level");
985 break;
986 }
987 port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
988 event, (uint8_t*) &currState->longDesc.data,
989 currState->tc->getCpuPtr()->clockPeriod(), flag);
990 DPRINTF(TLBVerbose,
991 "Adding to walker fifo: queue size before adding: %d\n",
992 stateQueues[start_lookup_level].size());
993 stateQueues[start_lookup_level].push_back(currState);
994 currState = NULL;
995 } else {
996 fetchDescriptor(desc_addr, (uint8_t*)&currState->longDesc.data,
997 sizeof(uint64_t), flag, -1, NULL,
998 &TableWalker::doLongDescriptor);
999 f = currState->fault;
1000 }
1001
1002 return f;
1003}
1004
1005void
1006TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1007 uint8_t texcb, bool s)
1008{
1009 // Note: tc and sctlr local variables are hiding tc and sctrl class
1010 // variables
1011 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
1012 te.shareable = false; // default value
1013 te.nonCacheable = false;
1014 te.outerShareable = false;
1015 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
1016 switch(texcb) {
1017 case 0: // Stongly-ordered
1018 te.nonCacheable = true;
1019 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1020 te.shareable = true;
1021 te.innerAttrs = 1;
1022 te.outerAttrs = 0;
1023 break;
1024 case 1: // Shareable Device
1025 te.nonCacheable = true;
1026 te.mtype = TlbEntry::MemoryType::Device;
1027 te.shareable = true;
1028 te.innerAttrs = 3;
1029 te.outerAttrs = 0;
1030 break;
1031 case 2: // Outer and Inner Write-Through, no Write-Allocate
1032 te.mtype = TlbEntry::MemoryType::Normal;
1033 te.shareable = s;
1034 te.innerAttrs = 6;
1035 te.outerAttrs = bits(texcb, 1, 0);
1036 break;
1037 case 3: // Outer and Inner Write-Back, no Write-Allocate
1038 te.mtype = TlbEntry::MemoryType::Normal;
1039 te.shareable = s;
1040 te.innerAttrs = 7;
1041 te.outerAttrs = bits(texcb, 1, 0);
1042 break;
1043 case 4: // Outer and Inner Non-cacheable
1044 te.nonCacheable = true;
1045 te.mtype = TlbEntry::MemoryType::Normal;
1046 te.shareable = s;
1047 te.innerAttrs = 0;
1048 te.outerAttrs = bits(texcb, 1, 0);
1049 break;
1050 case 5: // Reserved
1051 panic("Reserved texcb value!\n");
1052 break;
1053 case 6: // Implementation Defined
1054 panic("Implementation-defined texcb value!\n");
1055 break;
1056 case 7: // Outer and Inner Write-Back, Write-Allocate
1057 te.mtype = TlbEntry::MemoryType::Normal;
1058 te.shareable = s;
1059 te.innerAttrs = 5;
1060 te.outerAttrs = 1;
1061 break;
1062 case 8: // Non-shareable Device
1063 te.nonCacheable = true;
1064 te.mtype = TlbEntry::MemoryType::Device;
1065 te.shareable = false;
1066 te.innerAttrs = 3;
1067 te.outerAttrs = 0;
1068 break;
1069 case 9 ... 15: // Reserved
1070 panic("Reserved texcb value!\n");
1071 break;
1072 case 16 ... 31: // Cacheable Memory
1073 te.mtype = TlbEntry::MemoryType::Normal;
1074 te.shareable = s;
1075 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0)
1076 te.nonCacheable = true;
1077 te.innerAttrs = bits(texcb, 1, 0);
1078 te.outerAttrs = bits(texcb, 3, 2);
1079 break;
1080 default:
1081 panic("More than 32 states for 5 bits?\n");
1082 }
1083 } else {
1084 assert(tc);
1085 PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR,
1086 currState->tc, !currState->isSecure));
1087 NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR,
1088 currState->tc, !currState->isSecure));
1089 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
1090 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
1091 switch(bits(texcb, 2,0)) {
1092 case 0:
1093 curr_tr = prrr.tr0;
1094 curr_ir = nmrr.ir0;
1095 curr_or = nmrr.or0;
1096 te.outerShareable = (prrr.nos0 == 0);
1097 break;
1098 case 1:
1099 curr_tr = prrr.tr1;
1100 curr_ir = nmrr.ir1;
1101 curr_or = nmrr.or1;
1102 te.outerShareable = (prrr.nos1 == 0);
1103 break;
1104 case 2:
1105 curr_tr = prrr.tr2;
1106 curr_ir = nmrr.ir2;
1107 curr_or = nmrr.or2;
1108 te.outerShareable = (prrr.nos2 == 0);
1109 break;
1110 case 3:
1111 curr_tr = prrr.tr3;
1112 curr_ir = nmrr.ir3;
1113 curr_or = nmrr.or3;
1114 te.outerShareable = (prrr.nos3 == 0);
1115 break;
1116 case 4:
1117 curr_tr = prrr.tr4;
1118 curr_ir = nmrr.ir4;
1119 curr_or = nmrr.or4;
1120 te.outerShareable = (prrr.nos4 == 0);
1121 break;
1122 case 5:
1123 curr_tr = prrr.tr5;
1124 curr_ir = nmrr.ir5;
1125 curr_or = nmrr.or5;
1126 te.outerShareable = (prrr.nos5 == 0);
1127 break;
1128 case 6:
1129 panic("Imp defined type\n");
1130 case 7:
1131 curr_tr = prrr.tr7;
1132 curr_ir = nmrr.ir7;
1133 curr_or = nmrr.or7;
1134 te.outerShareable = (prrr.nos7 == 0);
1135 break;
1136 }
1137
1138 switch(curr_tr) {
1139 case 0:
1140 DPRINTF(TLBVerbose, "StronglyOrdered\n");
1141 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1142 te.nonCacheable = true;
1143 te.innerAttrs = 1;
1144 te.outerAttrs = 0;
1145 te.shareable = true;
1146 break;
1147 case 1:
1148 DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n",
1149 prrr.ds1, prrr.ds0, s);
1150 te.mtype = TlbEntry::MemoryType::Device;
1151 te.nonCacheable = true;
1152 te.innerAttrs = 3;
1153 te.outerAttrs = 0;
1154 if (prrr.ds1 && s)
1155 te.shareable = true;
1156 if (prrr.ds0 && !s)
1157 te.shareable = true;
1158 break;
1159 case 2:
1160 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n",
1161 prrr.ns1, prrr.ns0, s);
1162 te.mtype = TlbEntry::MemoryType::Normal;
1163 if (prrr.ns1 && s)
1164 te.shareable = true;
1165 if (prrr.ns0 && !s)
1166 te.shareable = true;
1167 break;
1168 case 3:
1169 panic("Reserved type");
1170 }
1171
1172 if (te.mtype == TlbEntry::MemoryType::Normal){
1173 switch(curr_ir) {
1174 case 0:
1175 te.nonCacheable = true;
1176 te.innerAttrs = 0;
1177 break;
1178 case 1:
1179 te.innerAttrs = 5;
1180 break;
1181 case 2:
1182 te.innerAttrs = 6;
1183 break;
1184 case 3:
1185 te.innerAttrs = 7;
1186 break;
1187 }
1188
1189 switch(curr_or) {
1190 case 0:
1191 te.nonCacheable = true;
1192 te.outerAttrs = 0;
1193 break;
1194 case 1:
1195 te.outerAttrs = 1;
1196 break;
1197 case 2:
1198 te.outerAttrs = 2;
1199 break;
1200 case 3:
1201 te.outerAttrs = 3;
1202 break;
1203 }
1204 }
1205 }
1206 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, "
1207 "outerAttrs: %d\n",
1208 te.shareable, te.innerAttrs, te.outerAttrs);
1209 te.setAttributes(false);
1210}
1211
1212void
1213TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
1214 LongDescriptor &lDescriptor)
1215{
1216 assert(_haveLPAE);
1217
1218 uint8_t attr;
1219 uint8_t sh = lDescriptor.sh();
1220 // Different format and source of attributes if this is a stage 2
1221 // translation
1222 if (isStage2) {
1223 attr = lDescriptor.memAttr();
1224 uint8_t attr_3_2 = (attr >> 2) & 0x3;
1225 uint8_t attr_1_0 = attr & 0x3;
1226
1227 DPRINTF(TLBVerbose, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr, sh);
1228
1229 if (attr_3_2 == 0) {
1230 te.mtype = attr_1_0 == 0 ? TlbEntry::MemoryType::StronglyOrdered
1231 : TlbEntry::MemoryType::Device;
1232 te.outerAttrs = 0;
1233 te.innerAttrs = attr_1_0 == 0 ? 1 : 3;
1234 te.nonCacheable = true;
1235 } else {
1236 te.mtype = TlbEntry::MemoryType::Normal;
1237 te.outerAttrs = attr_3_2 == 1 ? 0 :
1238 attr_3_2 == 2 ? 2 : 1;
1239 te.innerAttrs = attr_1_0 == 1 ? 0 :
1240 attr_1_0 == 2 ? 6 : 5;
1241 te.nonCacheable = (attr_3_2 == 1) || (attr_1_0 == 1);
1242 }
1243 } else {
1244 uint8_t attrIndx = lDescriptor.attrIndx();
1245
1246 // LPAE always uses remapping of memory attributes, irrespective of the
1247 // value of SCTLR.TRE
1248 MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
1249 int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc,
1250 !currState->isSecure);
1251 uint32_t mair = currState->tc->readMiscReg(reg_as_int);
1252 attr = (mair >> (8 * (attrIndx % 4))) & 0xff;
1253 uint8_t attr_7_4 = bits(attr, 7, 4);
1254 uint8_t attr_3_0 = bits(attr, 3, 0);
1255 DPRINTF(TLBVerbose, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx, sh, attr);
1256
1257 // Note: the memory subsystem only cares about the 'cacheable' memory
1258 // attribute. The other attributes are only used to fill the PAR register
1259 // accordingly to provide the illusion of full support
1260 te.nonCacheable = false;
1261
1262 switch (attr_7_4) {
1263 case 0x0:
1264 // Strongly-ordered or Device memory
1265 if (attr_3_0 == 0x0)
1266 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1267 else if (attr_3_0 == 0x4)
1268 te.mtype = TlbEntry::MemoryType::Device;
1269 else
1270 panic("Unpredictable behavior\n");
1271 te.nonCacheable = true;
1272 te.outerAttrs = 0;
1273 break;
1274 case 0x4:
1275 // Normal memory, Outer Non-cacheable
1276 te.mtype = TlbEntry::MemoryType::Normal;
1277 te.outerAttrs = 0;
1278 if (attr_3_0 == 0x4)
1279 // Inner Non-cacheable
1280 te.nonCacheable = true;
1281 else if (attr_3_0 < 0x8)
1282 panic("Unpredictable behavior\n");
1283 break;
1284 case 0x8:
1285 case 0x9:
1286 case 0xa:
1287 case 0xb:
1288 case 0xc:
1289 case 0xd:
1290 case 0xe:
1291 case 0xf:
1292 if (attr_7_4 & 0x4) {
1293 te.outerAttrs = (attr_7_4 & 1) ? 1 : 3;
1294 } else {
1295 te.outerAttrs = 0x2;
1296 }
1297 // Normal memory, Outer Cacheable
1298 te.mtype = TlbEntry::MemoryType::Normal;
1299 if (attr_3_0 != 0x4 && attr_3_0 < 0x8)
1300 panic("Unpredictable behavior\n");
1301 break;
1302 default:
1303 panic("Unpredictable behavior\n");
1304 break;
1305 }
1306
1307 switch (attr_3_0) {
1308 case 0x0:
1309 te.innerAttrs = 0x1;
1310 break;
1311 case 0x4:
1312 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0;
1313 break;
1314 case 0x8:
1315 case 0x9:
1316 case 0xA:
1317 case 0xB:
1318 te.innerAttrs = 6;
1319 break;
1320 case 0xC:
1321 case 0xD:
1322 case 0xE:
1323 case 0xF:
1324 te.innerAttrs = attr_3_0 & 1 ? 0x5 : 0x7;
1325 break;
1326 default:
1327 panic("Unpredictable behavior\n");
1328 break;
1329 }
1330 }
1331
1332 te.outerShareable = sh == 2;
1333 te.shareable = (sh & 0x2) ? true : false;
1334 te.setAttributes(true);
1335 te.attributes |= (uint64_t) attr << 56;
1336}
1337
1338void
1339TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx,
1340 uint8_t sh)
1341{
1342 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh);
1343
1344 // Select MAIR
1345 uint64_t mair;
1346 switch (currState->el) {
1347 case EL0:
1348 case EL1:
1349 mair = tc->readMiscReg(MISCREG_MAIR_EL1);
1350 break;
1351 case EL2:
1352 mair = tc->readMiscReg(MISCREG_MAIR_EL2);
1353 break;
1354 case EL3:
1355 mair = tc->readMiscReg(MISCREG_MAIR_EL3);
1356 break;
1357 default:
1358 panic("Invalid exception level");
1359 break;
1360 }
1361
1362 // Select attributes
1363 uint8_t attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx);
1364 uint8_t attr_lo = bits(attr, 3, 0);
1365 uint8_t attr_hi = bits(attr, 7, 4);
1366
1367 // Memory type
1368 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal;
1369
1370 // Cacheability
1371 te.nonCacheable = false;
1372 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory
1373 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable
1374 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable
1375 te.nonCacheable = true;
1376 }
1377
1378 te.shareable = sh == 2;
1379 te.outerShareable = (sh & 0x2) ? true : false;
1380 // Attributes formatted according to the 64-bit PAR
1381 te.attributes = ((uint64_t) attr << 56) |
1382 (1 << 11) | // LPAE bit
1383 (te.ns << 9) | // NS bit
1384 (sh << 7);
1385}
1386
1387void
1388TableWalker::doL1Descriptor()
1389{
1390 if (currState->fault != NoFault) {
1391 return;
1392 }
1393
1394 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
1395 currState->vaddr_tainted, currState->l1Desc.data);
1396 TlbEntry te;
1397
1398 switch (currState->l1Desc.type()) {
1399 case L1Descriptor::Ignore:
1400 case L1Descriptor::Reserved:
1401 if (!currState->timing) {
1402 currState->tc = NULL;
1403 currState->req = NULL;
1404 }
1405 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
1406 if (currState->isFetch)
1407 currState->fault =
1408 std::make_shared<PrefetchAbort>(
1409 currState->vaddr_tainted,
1410 ArmFault::TranslationLL + L1,
1411 isStage2,
1412 ArmFault::VmsaTran);
1413 else
1414 currState->fault =
1415 std::make_shared<DataAbort>(
1416 currState->vaddr_tainted,
1417 TlbEntry::DomainType::NoAccess,
1418 currState->isWrite,
1419 ArmFault::TranslationLL + L1, isStage2,
1420 ArmFault::VmsaTran);
1421 return;
1422 case L1Descriptor::Section:
1423 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
1424 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
1425 * enabled if set, do l1.Desc.setAp0() instead of generating
1426 * AccessFlag0
1427 */
1428
1429 currState->fault = std::make_shared<DataAbort>(
1430 currState->vaddr_tainted,
1431 currState->l1Desc.domain(),
1432 currState->isWrite,
1433 ArmFault::AccessFlagLL + L1,
1434 isStage2,
1435 ArmFault::VmsaTran);
1436 }
1437 if (currState->l1Desc.supersection()) {
1438 panic("Haven't implemented supersections\n");
1439 }
1440 insertTableEntry(currState->l1Desc, false);
1441 return;
1442 case L1Descriptor::PageTable:
1443 {
1444 Addr l2desc_addr;
1445 l2desc_addr = currState->l1Desc.l2Addr() |
1446 (bits(currState->vaddr, 19, 12) << 2);
1447 DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n",
1448 l2desc_addr, currState->isSecure ? "s" : "ns");
1449
1450 // Trickbox address check
1451 currState->fault = testWalk(l2desc_addr, sizeof(uint32_t),
1452 currState->l1Desc.domain(), L2);
1453
1454 if (currState->fault) {
1455 if (!currState->timing) {
1456 currState->tc = NULL;
1457 currState->req = NULL;
1458 }
1459 return;
1460 }
1461
1462 Request::Flags flag = Request::PT_WALK;
1463 if (currState->isSecure)
1464 flag.set(Request::SECURE);
1465
1466 bool delayed;
1467 delayed = fetchDescriptor(l2desc_addr,
1468 (uint8_t*)&currState->l2Desc.data,
1469 sizeof(uint32_t), flag, -1, &doL2DescEvent,
1470 &TableWalker::doL2Descriptor);
1471 if (delayed) {
1472 currState->delayed = true;
1473 }
1474
1475 return;
1476 }
1477 default:
1478 panic("A new type in a 2 bit field?\n");
1479 }
1480}
1481
1482void
1483TableWalker::doLongDescriptor()
1484{
1485 if (currState->fault != NoFault) {
1486 return;
1487 }
1488
1489 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n",
1490 currState->longDesc.lookupLevel, currState->vaddr_tainted,
1491 currState->longDesc.data,
1492 currState->aarch64 ? "AArch64" : "long-desc.");
1493
1494 if ((currState->longDesc.type() == LongDescriptor::Block) ||
1495 (currState->longDesc.type() == LongDescriptor::Page)) {
1496 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, "
1497 "xn: %d, ap: %d, af: %d, type: %d\n",
1498 currState->longDesc.lookupLevel,
1499 currState->longDesc.data,
1500 currState->longDesc.pxn(),
1501 currState->longDesc.xn(),
1502 currState->longDesc.ap(),
1503 currState->longDesc.af(),
1504 currState->longDesc.type());
1505 } else {
1506 DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n",
1507 currState->longDesc.lookupLevel,
1508 currState->longDesc.data,
1509 currState->longDesc.type());
1510 }
1511
1512 TlbEntry te;
1513
1514 switch (currState->longDesc.type()) {
1515 case LongDescriptor::Invalid:
1516 if (!currState->timing) {
1517 currState->tc = NULL;
1518 currState->req = NULL;
1519 }
1520
1521 DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n",
1522 currState->longDesc.lookupLevel,
1523 ArmFault::TranslationLL + currState->longDesc.lookupLevel);
1524 if (currState->isFetch)
1525 currState->fault = std::make_shared<PrefetchAbort>(
1526 currState->vaddr_tainted,
1527 ArmFault::TranslationLL + currState->longDesc.lookupLevel,
1528 isStage2,
1529 ArmFault::LpaeTran);
1530 else
1531 currState->fault = std::make_shared<DataAbort>(
1532 currState->vaddr_tainted,
1533 TlbEntry::DomainType::NoAccess,
1534 currState->isWrite,
1535 ArmFault::TranslationLL + currState->longDesc.lookupLevel,
1536 isStage2,
1537 ArmFault::LpaeTran);
1538 return;
1539 case LongDescriptor::Block:
1540 case LongDescriptor::Page:
1541 {
1542 bool fault = false;
1543 bool aff = false;
1544 // Check for address size fault
1545 if (checkAddrSizeFaultAArch64(
1546 mbits(currState->longDesc.data, MaxPhysAddrRange - 1,
1547 currState->longDesc.offsetBits()),
1548 currState->physAddrRange)) {
1549 fault = true;
1550 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n",
1551 currState->longDesc.lookupLevel);
1552 // Check for access fault
1553 } else if (currState->longDesc.af() == 0) {
1554 fault = true;
1555 DPRINTF(TLB, "L%d descriptor causing Access Fault\n",
1556 currState->longDesc.lookupLevel);
1557 aff = true;
1558 }
1559 if (fault) {
1560 if (currState->isFetch)
1561 currState->fault = std::make_shared<PrefetchAbort>(
1562 currState->vaddr_tainted,
1563 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) +
1564 currState->longDesc.lookupLevel,
1565 isStage2,
1566 ArmFault::LpaeTran);
1567 else
1568 currState->fault = std::make_shared<DataAbort>(
1569 currState->vaddr_tainted,
1570 TlbEntry::DomainType::NoAccess, currState->isWrite,
1571 (aff ? ArmFault::AccessFlagLL : ArmFault::AddressSizeLL) +
1572 currState->longDesc.lookupLevel,
1573 isStage2,
1574 ArmFault::LpaeTran);
1575 } else {
1576 insertTableEntry(currState->longDesc, true);
1577 }
1578 }
1579 return;
1580 case LongDescriptor::Table:
1581 {
1582 // Set hierarchical permission flags
1583 currState->secureLookup = currState->secureLookup &&
1584 currState->longDesc.secureTable();
1585 currState->rwTable = currState->rwTable &&
1586 currState->longDesc.rwTable();
1587 currState->userTable = currState->userTable &&
1588 currState->longDesc.userTable();
1589 currState->xnTable = currState->xnTable ||
1590 currState->longDesc.xnTable();
1591 currState->pxnTable = currState->pxnTable ||
1592 currState->longDesc.pxnTable();
1593
1594 // Set up next level lookup
1595 Addr next_desc_addr = currState->longDesc.nextDescAddr(
1596 currState->vaddr);
1597
1598 DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n",
1599 currState->longDesc.lookupLevel,
1600 currState->longDesc.lookupLevel + 1,
1601 next_desc_addr,
1602 currState->secureLookup ? "s" : "ns");
1603
1604 // Check for address size fault
1605 if (currState->aarch64 && checkAddrSizeFaultAArch64(
1606 next_desc_addr, currState->physAddrRange)) {
1607 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n",
1608 currState->longDesc.lookupLevel);
1609 if (currState->isFetch)
1610 currState->fault = std::make_shared<PrefetchAbort>(
1611 currState->vaddr_tainted,
1612 ArmFault::AddressSizeLL
1613 + currState->longDesc.lookupLevel,
1614 isStage2,
1615 ArmFault::LpaeTran);
1616 else
1617 currState->fault = std::make_shared<DataAbort>(
1618 currState->vaddr_tainted,
1619 TlbEntry::DomainType::NoAccess, currState->isWrite,
1620 ArmFault::AddressSizeLL
1621 + currState->longDesc.lookupLevel,
1622 isStage2,
1623 ArmFault::LpaeTran);
1624 return;
1625 }
1626
1627 // Trickbox address check
1628 currState->fault = testWalk(
1629 next_desc_addr, sizeof(uint64_t), TlbEntry::DomainType::Client,
1630 toLookupLevel(currState->longDesc.lookupLevel +1));
1631
1632 if (currState->fault) {
1633 if (!currState->timing) {
1634 currState->tc = NULL;
1635 currState->req = NULL;
1636 }
1637 return;
1638 }
1639
1640 Request::Flags flag = Request::PT_WALK;
1641 if (currState->secureLookup)
1642 flag.set(Request::SECURE);
1643
1644 currState->longDesc.lookupLevel =
1645 (LookupLevel) (currState->longDesc.lookupLevel + 1);
1646 Event *event = NULL;
1647 switch (currState->longDesc.lookupLevel) {
1648 case L1:
1649 assert(currState->aarch64);
1650 event = &doL1LongDescEvent;
1651 break;
1652 case L2:
1653 event = &doL2LongDescEvent;
1654 break;
1655 case L3:
1656 event = &doL3LongDescEvent;
1657 break;
1658 default:
1659 panic("Wrong lookup level in table walk\n");
1660 break;
1661 }
1662
1663 bool delayed;
1664 delayed = fetchDescriptor(next_desc_addr, (uint8_t*)&currState->longDesc.data,
1665 sizeof(uint64_t), flag, -1, event,
1666 &TableWalker::doLongDescriptor);
1667 if (delayed) {
1668 currState->delayed = true;
1669 }
1670 }
1671 return;
1672 default:
1673 panic("A new type in a 2 bit field?\n");
1674 }
1675}
1676
1677void
1678TableWalker::doL2Descriptor()
1679{
1680 if (currState->fault != NoFault) {
1681 return;
1682 }
1683
1684 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
1685 currState->vaddr_tainted, currState->l2Desc.data);
1686 TlbEntry te;
1687
1688 if (currState->l2Desc.invalid()) {
1689 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
1690 if (!currState->timing) {
1691 currState->tc = NULL;
1692 currState->req = NULL;
1693 }
1694 if (currState->isFetch)
1695 currState->fault = std::make_shared<PrefetchAbort>(
1696 currState->vaddr_tainted,
1697 ArmFault::TranslationLL + L2,
1698 isStage2,
1699 ArmFault::VmsaTran);
1700 else
1701 currState->fault = std::make_shared<DataAbort>(
1702 currState->vaddr_tainted, currState->l1Desc.domain(),
1703 currState->isWrite, ArmFault::TranslationLL + L2,
1704 isStage2,
1705 ArmFault::VmsaTran);
1706 return;
1707 }
1708
1709 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {
1710 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
1711 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0
1712 */
1713 DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n",
1714 currState->sctlr.afe, currState->l2Desc.ap());
1715
1716 currState->fault = std::make_shared<DataAbort>(
1717 currState->vaddr_tainted,
1718 TlbEntry::DomainType::NoAccess, currState->isWrite,
1719 ArmFault::AccessFlagLL + L2, isStage2,
1720 ArmFault::VmsaTran);
1721 }
1722
1723 insertTableEntry(currState->l2Desc, false);
1724}
1725
1726void
1727TableWalker::doL1DescriptorWrapper()
1728{
1729 currState = stateQueues[L1].front();
1730 currState->delayed = false;
1731 // if there's a stage2 translation object we don't need it any more
1732 if (currState->stage2Tran) {
1733 delete currState->stage2Tran;
1734 currState->stage2Tran = NULL;
1735 }
1736
1737
1738 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
1739 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
1740
1741 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr_tainted);
1742 doL1Descriptor();
1743
1744 stateQueues[L1].pop_front();
1745 // Check if fault was generated
1746 if (currState->fault != NoFault) {
1747 currState->transState->finish(currState->fault, currState->req,
1748 currState->tc, currState->mode);
1749 statWalksShortTerminatedAtLevel[0]++;
1750
1751 pending = false;
1752 nextWalk(currState->tc);
1753
1754 currState->req = NULL;
1755 currState->tc = NULL;
1756 currState->delayed = false;
1757 delete currState;
1758 }
1759 else if (!currState->delayed) {
1760 // delay is not set so there is no L2 to do
1761 // Don't finish the translation if a stage 2 look up is underway
1762 if (!currState->doingStage2) {
1763 statWalkServiceTime.sample(curTick() - currState->startTime);
1764 DPRINTF(TLBVerbose, "calling translateTiming again\n");
1765 currState->fault = tlb->translateTiming(currState->req, currState->tc,
1766 currState->transState, currState->mode);
1767 statWalksShortTerminatedAtLevel[0]++;
1768 }
1769
1770 pending = false;
1771 nextWalk(currState->tc);
1772
1773 currState->req = NULL;
1774 currState->tc = NULL;
1775 currState->delayed = false;
1776 delete currState;
1777 } else {
1778 // need to do L2 descriptor
1779 stateQueues[L2].push_back(currState);
1780 }
1781 currState = NULL;
1782}
1783
1784void
1785TableWalker::doL2DescriptorWrapper()
1786{
1787 currState = stateQueues[L2].front();
1788 assert(currState->delayed);
1789 // if there's a stage2 translation object we don't need it any more
1790 if (currState->stage2Tran) {
1791 delete currState->stage2Tran;
1792 currState->stage2Tran = NULL;
1793 }
1794
1795 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
1796 currState->vaddr_tainted);
1797 doL2Descriptor();
1798
1799 // Check if fault was generated
1800 if (currState->fault != NoFault) {
1801 currState->transState->finish(currState->fault, currState->req,
1802 currState->tc, currState->mode);
1803 statWalksShortTerminatedAtLevel[1]++;
1804 }
1805 else {
1806 // Don't finish the translation if a stage 2 look up is underway
1807 if (!currState->doingStage2) {
1808 statWalkServiceTime.sample(curTick() - currState->startTime);
1809 DPRINTF(TLBVerbose, "calling translateTiming again\n");
1810 currState->fault = tlb->translateTiming(currState->req,
1811 currState->tc, currState->transState, currState->mode);
1812 statWalksShortTerminatedAtLevel[1]++;
1813 }
1814 }
1815
1816
1817 stateQueues[L2].pop_front();
1818 pending = false;
1819 nextWalk(currState->tc);
1820
1821 currState->req = NULL;
1822 currState->tc = NULL;
1823 currState->delayed = false;
1824
1825 delete currState;
1826 currState = NULL;
1827}
1828
1829void
1830TableWalker::doL0LongDescriptorWrapper()
1831{
1832 doLongDescriptorWrapper(L0);
1833}
1834
1835void
1836TableWalker::doL1LongDescriptorWrapper()
1837{
1838 doLongDescriptorWrapper(L1);
1839}
1840
1841void
1842TableWalker::doL2LongDescriptorWrapper()
1843{
1844 doLongDescriptorWrapper(L2);
1845}
1846
1847void
1848TableWalker::doL3LongDescriptorWrapper()
1849{
1850 doLongDescriptorWrapper(L3);
1851}
1852
1853void
1854TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level)
1855{
1856 currState = stateQueues[curr_lookup_level].front();
1857 assert(curr_lookup_level == currState->longDesc.lookupLevel);
1858 currState->delayed = false;
1859
1860 // if there's a stage2 translation object we don't need it any more
1861 if (currState->stage2Tran) {
1862 delete currState->stage2Tran;
1863 currState->stage2Tran = NULL;
1864 }
1865
1866 DPRINTF(TLBVerbose, "calling doLongDescriptor for vaddr:%#x\n",
1867 currState->vaddr_tainted);
1868 doLongDescriptor();
1869
1870 stateQueues[curr_lookup_level].pop_front();
1871
1872 if (currState->fault != NoFault) {
1873 // A fault was generated
1874 currState->transState->finish(currState->fault, currState->req,
1875 currState->tc, currState->mode);
1876
1877 pending = false;
1878 nextWalk(currState->tc);
1879
1880 currState->req = NULL;
1881 currState->tc = NULL;
1882 currState->delayed = false;
1883 delete currState;
1884 } else if (!currState->delayed) {
1885 // No additional lookups required
1886 // Don't finish the translation if a stage 2 look up is underway
1887 if (!currState->doingStage2) {
1888 DPRINTF(TLBVerbose, "calling translateTiming again\n");
1889 statWalkServiceTime.sample(curTick() - currState->startTime);
1890 currState->fault = tlb->translateTiming(currState->req, currState->tc,
1891 currState->transState,
1892 currState->mode);
1893 statWalksLongTerminatedAtLevel[(unsigned) curr_lookup_level]++;
1894 }
1895
1896 pending = false;
1897 nextWalk(currState->tc);
1898
1899 currState->req = NULL;
1900 currState->tc = NULL;
1901 currState->delayed = false;
1902 delete currState;
1903 } else {
1904 if (curr_lookup_level >= MAX_LOOKUP_LEVELS - 1)
1905 panic("Max. number of lookups already reached in table walk\n");
1906 // Need to perform additional lookups
1907 stateQueues[currState->longDesc.lookupLevel].push_back(currState);
1908 }
1909 currState = NULL;
1910}
1911
1912
1913void
1914TableWalker::nextWalk(ThreadContext *tc)
1915{
1916 if (pendingQueue.size())
1917 schedule(doProcessEvent, clockEdge(Cycles(1)));
1918 else
1919 completeDrain();
1920}
1921
1922bool
1923TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
1924 Request::Flags flags, int queueIndex, Event *event,
1925 void (TableWalker::*doDescriptor)())
1926{
1927 bool isTiming = currState->timing;
1928
1929 DPRINTF(TLBVerbose, "Fetching descriptor at address: 0x%x stage2Req: %d\n",
1930 descAddr, currState->stage2Req);
1931
1932 // If this translation has a stage 2 then we know descAddr is an IPA and
1933 // needs to be translated before we can access the page table. Do that
1934 // check here.
1935 if (currState->stage2Req) {
1936 Fault fault;
1937 flags = flags | TLB::MustBeOne;
1938
1939 if (isTiming) {
1940 Stage2MMU::Stage2Translation *tran = new
1941 Stage2MMU::Stage2Translation(*stage2Mmu, data, event,
1942 currState->vaddr);
1943 currState->stage2Tran = tran;
1944 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes,
1945 flags);
1946 fault = tran->fault;
1947 } else {
1948 fault = stage2Mmu->readDataUntimed(currState->tc,
1949 currState->vaddr, descAddr, data, numBytes, flags,
1950 currState->functional);
1951 }
1952
1953 if (fault != NoFault) {
1954 currState->fault = fault;
1955 }
1956 if (isTiming) {
1957 if (queueIndex >= 0) {
1958 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
1959 stateQueues[queueIndex].size());
1960 stateQueues[queueIndex].push_back(currState);
1961 currState = NULL;
1962 }
1963 } else {
1964 (this->*doDescriptor)();
1965 }
1966 } else {
1967 if (isTiming) {
1968 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data,
1969 currState->tc->getCpuPtr()->clockPeriod(),flags);
1970 if (queueIndex >= 0) {
1971 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
1972 stateQueues[queueIndex].size());
1973 stateQueues[queueIndex].push_back(currState);
1974 currState = NULL;
1975 }
1976 } else if (!currState->functional) {
1977 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data,
1978 currState->tc->getCpuPtr()->clockPeriod(), flags);
1979 (this->*doDescriptor)();
1980 } else {
1981 RequestPtr req = new Request(descAddr, numBytes, flags, masterId);
1982 req->taskId(ContextSwitchTaskId::DMA);
1983 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
1984 pkt->dataStatic(data);
1985 port->sendFunctional(pkt);
1986 (this->*doDescriptor)();
1987 delete req;
1988 delete pkt;
1989 }
1990 }
1991 return (isTiming);
1992}
1993
1994void
1995TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
1996{
1997 TlbEntry te;
1998
1999 // Create and fill a new page table entry
2000 te.valid = true;
2001 te.longDescFormat = longDescriptor;
2002 te.isHyp = currState->isHyp;
2003 te.asid = currState->asid;
2004 te.vmid = currState->vmid;
2005 te.N = descriptor.offsetBits();
2006 te.vpn = currState->vaddr >> te.N;
2007 te.size = (1<<te.N) - 1;
2008 te.pfn = descriptor.pfn();
2009 te.domain = descriptor.domain();
2010 te.lookupLevel = descriptor.lookupLevel;
2011 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2;
2012 te.nstid = !currState->isSecure;
2013 te.xn = descriptor.xn();
2014 if (currState->aarch64)
2015 te.el = currState->el;
2016 else
2017 te.el = 1;
2018
2019 statPageSizes[pageSizeNtoStatBin(te.N)]++;
2020 statRequestOrigin[COMPLETED][currState->isFetch]++;
2021
2022 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries
2023 // as global
2024 te.global = descriptor.global(currState) || isStage2;
2025 if (longDescriptor) {
2026 LongDescriptor lDescriptor =
2027 dynamic_cast<LongDescriptor &>(descriptor);
2028
2029 te.xn |= currState->xnTable;
2030 te.pxn = currState->pxnTable || lDescriptor.pxn();
2031 if (isStage2) {
2032 // this is actually the HAP field, but its stored in the same bit
2033 // possitions as the AP field in a stage 1 translation.
2034 te.hap = lDescriptor.ap();
2035 } else {
2036 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) |
2037 (currState->userTable && (descriptor.ap() & 0x1));
2038 }
2039 if (currState->aarch64)
2040 memAttrsAArch64(currState->tc, te, currState->longDesc.attrIndx(),
2041 currState->longDesc.sh());
2042 else
2043 memAttrsLPAE(currState->tc, te, lDescriptor);
2044 } else {
2045 te.ap = descriptor.ap();
2046 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),
2047 descriptor.shareable());
2048 }
2049
2050 // Debug output
2051 DPRINTF(TLB, descriptor.dbgHeader().c_str());
2052 DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
2053 te.N, te.pfn, te.size, te.global, te.valid);
2054 DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
2055 "vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
2056 te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp,
2057 te.nonCacheable, te.ns);
2058 DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n",
2059 descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()),
2060 descriptor.getRawData());
2061
2062 // Insert the entry into the TLB
2063 tlb->insert(currState->vaddr, te);
2064 if (!currState->timing) {
2065 currState->tc = NULL;
2066 currState->req = NULL;
2067 }
2068}
2069
2070ArmISA::TableWalker *
2071ArmTableWalkerParams::create()
2072{
2073 return new ArmISA::TableWalker(this);
2074}
2075
2076LookupLevel
2077TableWalker::toLookupLevel(uint8_t lookup_level_as_int)
2078{
2079 switch (lookup_level_as_int) {
2080 case L1:
2081 return L1;
2082 case L2:
2083 return L2;
2084 case L3:
2085 return L3;
2086 default:
2087 panic("Invalid lookup level conversion");
2088 }
2089}
2090
2091/* this method keeps track of the table walker queue's residency, so
2092 * needs to be called whenever requests start and complete. */
2093void
2094TableWalker::pendingChange()
2095{
2096 unsigned n = pendingQueue.size();
2097 if ((currState != NULL) && (currState != pendingQueue.front())) {
2098 ++n;
2099 }
2100
2101 if (n != pendingReqs) {
2102 Tick now = curTick();
2103 statPendingWalks.sample(pendingReqs, now - pendingChangeTick);
2104 pendingReqs = n;
2105 pendingChangeTick = now;
2106 }
2107}
2108
2109Fault
2110TableWalker::testWalk(Addr pa, Addr size, TlbEntry::DomainType domain,
2111 LookupLevel lookup_level)
2112{
2113 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure,
2114 currState->mode, domain, lookup_level);
2115}
2116
2117
2118uint8_t
2119TableWalker::pageSizeNtoStatBin(uint8_t N)
2120{
2121 /* for statPageSizes */
2122 switch(N) {
2123 case 12: return 0; // 4K
2124 case 14: return 1; // 16K (using 16K granule in v8-64)
2125 case 16: return 2; // 64K
2126 case 20: return 3; // 1M
2127 case 21: return 4; // 2M-LPAE
2128 case 24: return 5; // 16M
2129 case 25: return 6; // 32M (using 16K granule in v8-64)
2130 case 29: return 7; // 512M (using 64K granule in v8-64)
2131 case 30: return 8; // 1G-LPAE
2132 default:
2133 panic("unknown page size");
2134 return 255;
2135 }
2136}
2137
2138void
2139TableWalker::regStats()
2140{
2141 ClockedObject::regStats();
2142
2143 statWalks
2144 .name(name() + ".walks")
2145 .desc("Table walker walks requested")
2146 ;
2147
2148 statWalksShortDescriptor
2149 .name(name() + ".walksShort")
2150 .desc("Table walker walks initiated with short descriptors")
2151 .flags(Stats::nozero)
2152 ;
2153
2154 statWalksLongDescriptor
2155 .name(name() + ".walksLong")
2156 .desc("Table walker walks initiated with long descriptors")
2157 .flags(Stats::nozero)
2158 ;
2159
2160 statWalksShortTerminatedAtLevel
2161 .init(2)
2162 .name(name() + ".walksShortTerminationLevel")
2163 .desc("Level at which table walker walks "
2164 "with short descriptors terminate")
2165 .flags(Stats::nozero)
2166 ;
2167 statWalksShortTerminatedAtLevel.subname(0, "Level1");
2168 statWalksShortTerminatedAtLevel.subname(1, "Level2");
2169
2170 statWalksLongTerminatedAtLevel
2171 .init(4)
2172 .name(name() + ".walksLongTerminationLevel")
2173 .desc("Level at which table walker walks "
2174 "with long descriptors terminate")
2175 .flags(Stats::nozero)
2176 ;
2177 statWalksLongTerminatedAtLevel.subname(0, "Level0");
2178 statWalksLongTerminatedAtLevel.subname(1, "Level1");
2179 statWalksLongTerminatedAtLevel.subname(2, "Level2");
2180 statWalksLongTerminatedAtLevel.subname(3, "Level3");
2181
2182 statSquashedBefore
2183 .name(name() + ".walksSquashedBefore")
2184 .desc("Table walks squashed before starting")
2185 .flags(Stats::nozero)
2186 ;
2187
2188 statSquashedAfter
2189 .name(name() + ".walksSquashedAfter")
2190 .desc("Table walks squashed after completion")
2191 .flags(Stats::nozero)
2192 ;
2193
2194 statWalkWaitTime
2195 .init(16)
2196 .name(name() + ".walkWaitTime")
2197 .desc("Table walker wait (enqueue to first request) latency")
2198 .flags(Stats::pdf | Stats::nozero | Stats::nonan)
2199 ;
2200
2201 statWalkServiceTime
2202 .init(16)
2203 .name(name() + ".walkCompletionTime")
2204 .desc("Table walker service (enqueue to completion) latency")
2205 .flags(Stats::pdf | Stats::nozero | Stats::nonan)
2206 ;
2207
2208 statPendingWalks
2209 .init(16)
2210 .name(name() + ".walksPending")
2211 .desc("Table walker pending requests distribution")
2212 .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan)
2213 ;
2214
2215 statPageSizes // see DDI 0487A D4-1661
2216 .init(9)
2217 .name(name() + ".walkPageSizes")
2218 .desc("Table walker page sizes translated")
2219 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero)
2220 ;
2221 statPageSizes.subname(0, "4K");
2222 statPageSizes.subname(1, "16K");
2223 statPageSizes.subname(2, "64K");
2224 statPageSizes.subname(3, "1M");
2225 statPageSizes.subname(4, "2M");
2226 statPageSizes.subname(5, "16M");
2227 statPageSizes.subname(6, "32M");
2228 statPageSizes.subname(7, "512M");
2229 statPageSizes.subname(8, "1G");
2230
2231 statRequestOrigin
2232 .init(2,2) // Instruction/Data, requests/completed
2233 .name(name() + ".walkRequestOrigin")
2234 .desc("Table walker requests started/completed, data/inst")
2235 .flags(Stats::total)
2236 ;
2237 statRequestOrigin.subname(0,"Requested");
2238 statRequestOrigin.subname(1,"Completed");
2239 statRequestOrigin.ysubname(0,"Data");
2240 statRequestOrigin.ysubname(1,"Inst");
2241}