1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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1337 te.innerAttrs = attr_lo == 0 ? 1 : 3;
1338 te.nonCacheable = true;
1339 } else {
1340 te.mtype = TlbEntry::MemoryType::Normal;
1341 te.outerAttrs = attr_hi == 1 ? 0 :
1342 attr_hi == 2 ? 2 : 1;
1343 te.innerAttrs = attr_lo == 1 ? 0 :
1344 attr_lo == 2 ? 6 : 5;
1345 te.nonCacheable = (attr_hi == 1) || (attr_lo == 1);
1346 }
1347 } else {
1348 uint8_t attrIndx = lDescriptor.attrIndx();
1349
1350 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh);
1351
1352 // Select MAIR
1353 uint64_t mair;

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1372 attr_lo = bits(attr, 3, 0);
1373 attr_hi = bits(attr, 7, 4);
1374
1375 // Memory type
1376 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal;
1377
1378 // Cacheability
1379 te.nonCacheable = false;
1380 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory
1381 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable
1382 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable
1383 te.nonCacheable = true;
1384 }
1385
1386 te.shareable = sh == 2;
1387 te.outerShareable = (sh & 0x2) ? true : false;
1388 // Attributes formatted according to the 64-bit PAR
1389 te.attributes = ((uint64_t) attr << 56) |
1390 (1 << 11) | // LPAE bit
1391 (te.ns << 9) | // NS bit
1392 (sh << 7);

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