1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1332
1333 te.outerShareable = sh == 2;
1334 te.shareable = (sh & 0x2) ? true : false;
1335 te.setAttributes(true);
1336 te.attributes |= (uint64_t) attr << 56;
1337}
1338
1339void
1340TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
1341 LongDescriptor &lDescriptor)
1342{
1343 uint8_t attr;
1344 uint8_t attr_hi;
1345 uint8_t attr_lo;
1346 uint8_t sh = lDescriptor.sh();
1347
1348 if (isStage2) {
1349 attr = lDescriptor.memAttr();
1350 uint8_t attr_hi = (attr >> 2) & 0x3;
1351 uint8_t attr_lo = attr & 0x3;
1352
1353 DPRINTF(TLBVerbose, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr, sh);
1354
1355 if (attr_hi == 0) {
1356 te.mtype = attr_lo == 0 ? TlbEntry::MemoryType::StronglyOrdered
1357 : TlbEntry::MemoryType::Device;
1358 te.outerAttrs = 0;
1359 te.innerAttrs = attr_lo == 0 ? 1 : 3;
1360 te.nonCacheable = true;
1361 } else {
1362 te.mtype = TlbEntry::MemoryType::Normal;
1363 te.outerAttrs = attr_hi == 1 ? 0 :
1364 attr_hi == 2 ? 2 : 1;
1365 te.innerAttrs = attr_lo == 1 ? 0 :
1366 attr_lo == 2 ? 6 : 5;
1367 te.nonCacheable = (attr_hi == 1) || (attr_lo == 1);
1368 }
1369 } else {
1370 uint8_t attrIndx = lDescriptor.attrIndx();
1371
1372 DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh);
1373
1374 // Select MAIR
1375 uint64_t mair;
1376 switch (currState->el) {
1377 case EL0:
1378 case EL1:
1379 mair = tc->readMiscReg(MISCREG_MAIR_EL1);
1380 break;
1381 case EL2:
1382 mair = tc->readMiscReg(MISCREG_MAIR_EL2);
1383 break;
1384 case EL3:
1385 mair = tc->readMiscReg(MISCREG_MAIR_EL3);
1386 break;
1387 default:
1388 panic("Invalid exception level");
1389 break;
1390 }
1391
1392 // Select attributes
1393 attr = bits(mair, 8 * attrIndx + 7, 8 * attrIndx);
1394 attr_lo = bits(attr, 3, 0);
1395 attr_hi = bits(attr, 7, 4);
1396
1397 // Memory type
1398 te.mtype = attr_hi == 0 ? TlbEntry::MemoryType::Device : TlbEntry::MemoryType::Normal;
1399
1400 // Cacheability
1401 te.nonCacheable = false;
1402 if (te.mtype == TlbEntry::MemoryType::Device || // Device memory
1403 attr_hi == 0x8 || // Normal memory, Outer Non-cacheable
1404 attr_lo == 0x8) { // Normal memory, Inner Non-cacheable
1405 te.nonCacheable = true;
1406 }
1407
1408 te.shareable = sh == 2;
1409 te.outerShareable = (sh & 0x2) ? true : false;
1410 // Attributes formatted according to the 64-bit PAR
1411 te.attributes = ((uint64_t) attr << 56) |
1412 (1 << 11) | // LPAE bit
1413 (te.ns << 9) | // NS bit
1414 (sh << 7);
1415 }
1416}
1417
1418void
1419TableWalker::doL1Descriptor()
1420{
1421 if (currState->fault != NoFault) {
1422 return;
1423 }

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2063 // this is actually the HAP field, but its stored in the same bit
2064 // possitions as the AP field in a stage 1 translation.
2065 te.hap = lDescriptor.ap();
2066 } else {
2067 te.ap = ((!currState->rwTable || descriptor.ap() >> 1) << 1) |
2068 (currState->userTable && (descriptor.ap() & 0x1));
2069 }
2070 if (currState->aarch64)
2071 memAttrsAArch64(currState->tc, te, lDescriptor);
2072 else
2073 memAttrsLPAE(currState->tc, te, lDescriptor);
2074 } else {
2075 te.ap = descriptor.ap();
2076 memAttrs(currState->tc, te, currState->sctlr, descriptor.texcb(),
2077 descriptor.shareable());
2078 }
2079

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