system.hh (8286:abc8ab4ddd93) system.hh (8527:6bac5b04d588)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 return dynamic_cast<const Params *>(_params);
74 }
75
76 ArmSystem(Params *p);
77 ~ArmSystem();
78
79 void initState();
80
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 64 unchanged lines hidden (view full) ---

73 return dynamic_cast<const Params *>(_params);
74 }
75
76 ArmSystem(Params *p);
77 ~ArmSystem();
78
79 void initState();
80
81 /** Check if an address should be uncacheable until all caches are enabled.
82 * This exits because coherence on some addresses at boot is maintained via
83 * sw coherence until the caches are enbaled. Since we don't support sw
84 * coherence operations in gem5, this is a method that allows a system
85 * type to designate certain addresses that should remain uncachebale
86 * for a while.
87 */
88 virtual bool adderBootUncacheable(Addr a) { return false; }
89
81 virtual Addr fixFuncEventAddr(Addr addr)
82 {
83 // Remove the low bit that thumb symbols have set
84 // but that aren't actually odd aligned
85 if (addr & 0x1)
86 return addr & ~1;
87 return addr;
88 }
89};
90
91#endif
92
90 virtual Addr fixFuncEventAddr(Addr addr)
91 {
92 // Remove the low bit that thumb symbols have set
93 // but that aren't actually odd aligned
94 if (addr & 0x1)
95 return addr & ~1;
96 return addr;
97 }
98};
99
100#endif
101