1/*
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2 * Copyright (c) 2010 ARM Limited
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2 * Copyright (c) 2010, 2012-2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <string> 47#include <vector> 48
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49#include "dev/arm/generic_timer.hh" |
50#include "kern/linux/events.hh" 51#include "params/ArmSystem.hh" 52#include "sim/sim_object.hh" 53#include "sim/system.hh" 54
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55class ThreadContext; 56 |
57class ArmSystem : public System 58{ 59 protected: 60 /** 61 * PC based event to skip the dprink() call and emulate its 62 * functionality 63 */ 64 Linux::DebugPrintkEvent *debugPrintkEvent; 65 66 /** 67 * Pointer to the bootloader object 68 */ 69 ObjectFile *bootldr; 70
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71 /** 72 * True if this system implements the Security Extensions 73 */ 74 const bool _haveSecurity; 75 76 /** 77 * True if this system implements the Large Physical Address Extension 78 */ 79 const bool _haveLPAE; 80 81 /** 82 * True if this system implements the virtualization Extensions 83 */ 84 const bool _haveVirtualization; 85 86 /** 87 * True if this system implements the Generic Timer extension 88 */ 89 const bool _haveGenericTimer; 90 91 /** 92 * Pointer to the Generic Timer wrapper. 93 */ 94 GenericTimer *_genericTimer; 95 96 /** 97 * True if the register width of the highest implemented exception level is 98 * 64 bits (ARMv8) 99 */ 100 bool _highestELIs64; 101 102 /** 103 * Reset address if the highest implemented exception level is 64 bits 104 * (ARMv8) 105 */ 106 const Addr _resetAddr64; 107 108 /** 109 * Supported physical address range in bits if the highest implemented 110 * exception level is 64 bits (ARMv8) 111 */ 112 const uint8_t _physAddrRange64; 113 114 /** 115 * True if ASID is 16 bits in AArch64 (ARMv8) 116 */ 117 const bool _haveLargeAsid64; 118 |
119 public: 120 typedef ArmSystemParams Params; 121 const Params * 122 params() const 123 { 124 return dynamic_cast<const Params *>(_params); 125 } 126 127 ArmSystem(Params *p); 128 ~ArmSystem(); 129 130 /** 131 * Initialise the system 132 */ 133 virtual void initState(); 134 135 /** Check if an address should be uncacheable until all caches are enabled. 136 * This exits because coherence on some addresses at boot is maintained via 137 * sw coherence until the caches are enbaled. Since we don't support sw 138 * coherence operations in gem5, this is a method that allows a system 139 * type to designate certain addresses that should remain uncachebale 140 * for a while. 141 */ 142 virtual bool adderBootUncacheable(Addr a) { return false; } 143 144 virtual Addr fixFuncEventAddr(Addr addr) 145 { 146 // Remove the low bit that thumb symbols have set 147 // but that aren't actually odd aligned 148 if (addr & 0x1) 149 return addr & ~1; 150 return addr; 151 } 152 153 /** true if this a multiprocessor system */ 154 bool multiProc;
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155 156 /** Returns true if this system implements the Security Extensions */ 157 bool haveSecurity() const { return _haveSecurity; } 158 159 /** Returns true if this system implements the Large Physical Address 160 * Extension */ 161 bool haveLPAE() const { return _haveLPAE; } 162 163 /** Returns true if this system implements the virtualization 164 * Extensions 165 */ 166 bool haveVirtualization() const { return _haveVirtualization; } 167 168 /** Returns true if this system implements the Generic Timer extension. */ 169 bool haveGenericTimer() const { return _haveGenericTimer; } 170 171 /** Sets the pointer to the Generic Timer. */ 172 void setGenericTimer(GenericTimer *generic_timer) 173 { 174 _genericTimer = generic_timer; 175 } 176 177 /** Returns a pointer to the system counter. */ 178 GenericTimer::SystemCounter *getSystemCounter() const; 179 180 /** Returns a pointer to the appropriate architected timer. */ 181 GenericTimer::ArchTimer *getArchTimer(int cpu_id) const; 182 183 /** Returns true if the register width of the highest implemented exception 184 * level is 64 bits (ARMv8) */ 185 bool highestELIs64() const { return _highestELIs64; } 186 187 /** Returns the highest implemented exception level */ 188 ExceptionLevel highestEL() const 189 { 190 if (_haveSecurity) 191 return EL3; 192 // @todo: uncomment this to enable Virtualization 193 // if (_haveVirtualization) 194 // return EL2; 195 return EL1; 196 } 197 198 /** Returns the reset address if the highest implemented exception level is 199 * 64 bits (ARMv8) */ 200 Addr resetAddr64() const { return _resetAddr64; } 201 202 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 203 bool haveLargeAsid64() const { return _haveLargeAsid64; } 204 205 /** Returns the supported physical address range in bits if the highest 206 * implemented exception level is 64 bits (ARMv8) */ 207 uint8_t physAddrRange64() const { return _physAddrRange64; } 208 209 /** Returns the supported physical address range in bits */ 210 uint8_t physAddrRange() const 211 { 212 if (_highestELIs64) 213 return _physAddrRange64; 214 if (_haveLPAE) 215 return 40; 216 return 32; 217 } 218 219 /** Returns the physical address mask */ 220 Addr physAddrMask() const 221 { 222 return mask(physAddrRange()); 223 } 224 225 /** Returns true if the system of a specific thread context implements the 226 * Security Extensions 227 */ 228 static bool haveSecurity(ThreadContext *tc); 229 230 /** Returns true if the system of a specific thread context implements the 231 * virtualization Extensions 232 */ 233 static bool haveVirtualization(ThreadContext *tc); 234 235 /** Returns true if the system of a specific thread context implements the 236 * Large Physical Address Extension 237 */ 238 static bool haveLPAE(ThreadContext *tc); 239 240 /** Returns true if the register width of the highest implemented exception 241 * level for the system of a specific thread context is 64 bits (ARMv8) 242 */ 243 static bool highestELIs64(ThreadContext *tc); 244 245 /** Returns the highest implemented exception level for the system of a 246 * specific thread context 247 */ 248 static ExceptionLevel highestEL(ThreadContext *tc); 249 250 /** Returns the reset address if the highest implemented exception level for 251 * the system of a specific thread context is 64 bits (ARMv8) 252 */ 253 static Addr resetAddr64(ThreadContext *tc); 254 255 /** Returns the supported physical address range in bits for the system of a 256 * specific thread context 257 */ 258 static uint8_t physAddrRange(ThreadContext *tc); 259 260 /** Returns the physical address mask for the system of a specific thread 261 * context 262 */ 263 static Addr physAddrMask(ThreadContext *tc); 264 265 /** Returns true if ASID is 16 bits for the system of a specific thread 266 * context while in AArch64 (ARMv8) */ 267 static bool haveLargeAsid64(ThreadContext *tc); 268 |
269}; 270 271#endif 272
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