3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <string> 47#include <vector> 48
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <string> 47#include <vector> 48
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68 public: 69 typedef ArmSystemParams Params; 70 const Params * 71 params() const 72 { 73 return dynamic_cast<const Params *>(_params); 74 } 75 76 ArmSystem(Params *p); 77 ~ArmSystem(); 78 79 /** 80 * Initialise the system 81 */ 82 virtual void initState(); 83 84 /** Check if an address should be uncacheable until all caches are enabled. 85 * This exits because coherence on some addresses at boot is maintained via 86 * sw coherence until the caches are enbaled. Since we don't support sw 87 * coherence operations in gem5, this is a method that allows a system 88 * type to designate certain addresses that should remain uncachebale 89 * for a while. 90 */ 91 virtual bool adderBootUncacheable(Addr a) { return false; } 92 93 virtual Addr fixFuncEventAddr(Addr addr) 94 { 95 // Remove the low bit that thumb symbols have set 96 // but that aren't actually odd aligned 97 if (addr & 0x1) 98 return addr & ~1; 99 return addr; 100 } 101 102 /** true if this a multiprocessor system */ 103 bool multiProc;
| 119 public: 120 typedef ArmSystemParams Params; 121 const Params * 122 params() const 123 { 124 return dynamic_cast<const Params *>(_params); 125 } 126 127 ArmSystem(Params *p); 128 ~ArmSystem(); 129 130 /** 131 * Initialise the system 132 */ 133 virtual void initState(); 134 135 /** Check if an address should be uncacheable until all caches are enabled. 136 * This exits because coherence on some addresses at boot is maintained via 137 * sw coherence until the caches are enbaled. Since we don't support sw 138 * coherence operations in gem5, this is a method that allows a system 139 * type to designate certain addresses that should remain uncachebale 140 * for a while. 141 */ 142 virtual bool adderBootUncacheable(Addr a) { return false; } 143 144 virtual Addr fixFuncEventAddr(Addr addr) 145 { 146 // Remove the low bit that thumb symbols have set 147 // but that aren't actually odd aligned 148 if (addr & 0x1) 149 return addr & ~1; 150 return addr; 151 } 152 153 /** true if this a multiprocessor system */ 154 bool multiProc;
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