1/* 2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <memory> 47#include <string> 48#include <vector> 49 50#include "kern/linux/events.hh" 51#include "params/ArmSystem.hh" 52#include "params/GenericArmSystem.hh" 53#include "sim/sim_object.hh" 54#include "sim/system.hh" 55 56class GenericTimer;
| 1/* 2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_SYSTEM_HH__ 44#define __ARCH_ARM_SYSTEM_HH__ 45 46#include <memory> 47#include <string> 48#include <vector> 49 50#include "kern/linux/events.hh" 51#include "params/ArmSystem.hh" 52#include "params/GenericArmSystem.hh" 53#include "sim/sim_object.hh" 54#include "sim/system.hh" 55 56class GenericTimer;
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198 /** Returns true if the register width of the highest implemented exception 199 * level is 64 bits (ARMv8) */ 200 bool highestELIs64() const { return _highestELIs64; } 201 202 /** Returns the highest implemented exception level */ 203 ExceptionLevel highestEL() const 204 { 205 if (_haveSecurity) 206 return EL3; 207 if (_haveVirtualization) 208 return EL2; 209 return EL1; 210 } 211 212 /** Returns the reset address if the highest implemented exception level is 213 * 64 bits (ARMv8) */ 214 Addr resetAddr() const { return _resetAddr; } 215 216 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 217 bool haveLargeAsid64() const { return _haveLargeAsid64; } 218 219 /** Returns the supported physical address range in bits if the highest 220 * implemented exception level is 64 bits (ARMv8) */ 221 uint8_t physAddrRange64() const { return _physAddrRange64; } 222 223 /** Returns the supported physical address range in bits */ 224 uint8_t physAddrRange() const 225 { 226 if (_highestELIs64) 227 return _physAddrRange64; 228 if (_haveLPAE) 229 return 40; 230 return 32; 231 } 232 233 /** Returns the physical address mask */ 234 Addr physAddrMask() const 235 { 236 return mask(physAddrRange()); 237 } 238 239 /** 240 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns 241 * an invalid/empty range if disabled. 242 */ 243 const AddrRange &m5opRange() const { return _m5opRange; } 244 245 /** Is Arm Semihosting support enabled? */ 246 bool haveSemihosting() const { return semihosting != nullptr; } 247 248 /** 249 * Returns a valid ArmSystem pointer if using ARM ISA, it fails 250 * otherwise. 251 */ 252 static ArmSystem* getArmSystem(ThreadContext *tc); 253 254 /** Returns true if the system of a specific thread context implements the 255 * Security Extensions 256 */ 257 static bool haveSecurity(ThreadContext *tc); 258 259 /** Returns true if the system of a specific thread context implements the 260 * virtualization Extensions 261 */ 262 static bool haveVirtualization(ThreadContext *tc); 263 264 /** Returns true if the system of a specific thread context implements the 265 * Large Physical Address Extension 266 */ 267 static bool haveLPAE(ThreadContext *tc); 268 269 /** Returns true if the register width of the highest implemented exception 270 * level for the system of a specific thread context is 64 bits (ARMv8) 271 */ 272 static bool highestELIs64(ThreadContext *tc); 273 274 /** Returns the highest implemented exception level for the system of a 275 * specific thread context 276 */ 277 static ExceptionLevel highestEL(ThreadContext *tc); 278 279 /** Return true if the system implements a specific exception level */ 280 static bool haveEL(ThreadContext *tc, ExceptionLevel el); 281 282 /** Returns the reset address if the highest implemented exception level 283 * for the system of a specific thread context is 64 bits (ARMv8) 284 */ 285 static Addr resetAddr(ThreadContext *tc); 286 287 /** Returns the supported physical address range in bits for the system of a 288 * specific thread context 289 */ 290 static uint8_t physAddrRange(ThreadContext *tc); 291 292 /** Returns the physical address mask for the system of a specific thread 293 * context 294 */ 295 static Addr physAddrMask(ThreadContext *tc); 296 297 /** Returns true if ASID is 16 bits for the system of a specific thread 298 * context while in AArch64 (ARMv8) */ 299 static bool haveLargeAsid64(ThreadContext *tc); 300 301 /** Is Arm Semihosting support enabled? */ 302 static bool haveSemihosting(ThreadContext *tc); 303 304 /** Make a Semihosting call from aarch64 */ 305 static uint64_t callSemihosting64(ThreadContext *tc, 306 uint32_t op, uint64_t param); 307 308 /** Make a Semihosting call from aarch32 */ 309 static uint32_t callSemihosting32(ThreadContext *tc, 310 uint32_t op, uint32_t param); 311}; 312 313class GenericArmSystem : public ArmSystem 314{ 315 public: 316 typedef GenericArmSystemParams Params; 317 const Params * 318 params() const 319 { 320 return dynamic_cast<const Params *>(_params); 321 } 322 323 GenericArmSystem(Params *p) : ArmSystem(p) {}; 324 virtual ~GenericArmSystem() {}; 325 326 /** 327 * Initialise the system 328 */ 329 virtual void initState(); 330}; 331 332#endif
| 209 /** Returns true if the register width of the highest implemented exception 210 * level is 64 bits (ARMv8) */ 211 bool highestELIs64() const { return _highestELIs64; } 212 213 /** Returns the highest implemented exception level */ 214 ExceptionLevel highestEL() const 215 { 216 if (_haveSecurity) 217 return EL3; 218 if (_haveVirtualization) 219 return EL2; 220 return EL1; 221 } 222 223 /** Returns the reset address if the highest implemented exception level is 224 * 64 bits (ARMv8) */ 225 Addr resetAddr() const { return _resetAddr; } 226 227 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 228 bool haveLargeAsid64() const { return _haveLargeAsid64; } 229 230 /** Returns the supported physical address range in bits if the highest 231 * implemented exception level is 64 bits (ARMv8) */ 232 uint8_t physAddrRange64() const { return _physAddrRange64; } 233 234 /** Returns the supported physical address range in bits */ 235 uint8_t physAddrRange() const 236 { 237 if (_highestELIs64) 238 return _physAddrRange64; 239 if (_haveLPAE) 240 return 40; 241 return 32; 242 } 243 244 /** Returns the physical address mask */ 245 Addr physAddrMask() const 246 { 247 return mask(physAddrRange()); 248 } 249 250 /** 251 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns 252 * an invalid/empty range if disabled. 253 */ 254 const AddrRange &m5opRange() const { return _m5opRange; } 255 256 /** Is Arm Semihosting support enabled? */ 257 bool haveSemihosting() const { return semihosting != nullptr; } 258 259 /** 260 * Returns a valid ArmSystem pointer if using ARM ISA, it fails 261 * otherwise. 262 */ 263 static ArmSystem* getArmSystem(ThreadContext *tc); 264 265 /** Returns true if the system of a specific thread context implements the 266 * Security Extensions 267 */ 268 static bool haveSecurity(ThreadContext *tc); 269 270 /** Returns true if the system of a specific thread context implements the 271 * virtualization Extensions 272 */ 273 static bool haveVirtualization(ThreadContext *tc); 274 275 /** Returns true if the system of a specific thread context implements the 276 * Large Physical Address Extension 277 */ 278 static bool haveLPAE(ThreadContext *tc); 279 280 /** Returns true if the register width of the highest implemented exception 281 * level for the system of a specific thread context is 64 bits (ARMv8) 282 */ 283 static bool highestELIs64(ThreadContext *tc); 284 285 /** Returns the highest implemented exception level for the system of a 286 * specific thread context 287 */ 288 static ExceptionLevel highestEL(ThreadContext *tc); 289 290 /** Return true if the system implements a specific exception level */ 291 static bool haveEL(ThreadContext *tc, ExceptionLevel el); 292 293 /** Returns the reset address if the highest implemented exception level 294 * for the system of a specific thread context is 64 bits (ARMv8) 295 */ 296 static Addr resetAddr(ThreadContext *tc); 297 298 /** Returns the supported physical address range in bits for the system of a 299 * specific thread context 300 */ 301 static uint8_t physAddrRange(ThreadContext *tc); 302 303 /** Returns the physical address mask for the system of a specific thread 304 * context 305 */ 306 static Addr physAddrMask(ThreadContext *tc); 307 308 /** Returns true if ASID is 16 bits for the system of a specific thread 309 * context while in AArch64 (ARMv8) */ 310 static bool haveLargeAsid64(ThreadContext *tc); 311 312 /** Is Arm Semihosting support enabled? */ 313 static bool haveSemihosting(ThreadContext *tc); 314 315 /** Make a Semihosting call from aarch64 */ 316 static uint64_t callSemihosting64(ThreadContext *tc, 317 uint32_t op, uint64_t param); 318 319 /** Make a Semihosting call from aarch32 */ 320 static uint32_t callSemihosting32(ThreadContext *tc, 321 uint32_t op, uint32_t param); 322}; 323 324class GenericArmSystem : public ArmSystem 325{ 326 public: 327 typedef GenericArmSystemParams Params; 328 const Params * 329 params() const 330 { 331 return dynamic_cast<const Params *>(_params); 332 } 333 334 GenericArmSystem(Params *p) : ArmSystem(p) {}; 335 virtual ~GenericArmSystem() {}; 336 337 /** 338 * Initialise the system 339 */ 340 virtual void initState(); 341}; 342 343#endif
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