1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61 protected:
62 /**
63 * PC based event to skip the dprink() call and emulate its
64 * functionality
65 */
66 Linux::DebugPrintkEvent *debugPrintkEvent;
67
68 /** Bootloaders */
69 std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71 /**
72 * Pointer to the bootloader object
73 */
74 ObjectFile *bootldr;
75
76 /**
77 * True if this system implements the Security Extensions
78 */
79 const bool _haveSecurity;
80
81 /**
82 * True if this system implements the Large Physical Address Extension
83 */
84 const bool _haveLPAE;
85
86 /**
87 * True if this system implements the virtualization Extensions
88 */
89 const bool _haveVirtualization;
90
91 /**
92 * True if this system implements the Crypto Extension
93 */
94 const bool _haveCrypto;
95
96 /**
97 * Pointer to the Generic Timer wrapper.
98 */
99 GenericTimer *_genericTimer;
100
101 /**
102 * Reset address (ARMv8)
103 */
104 const Addr _resetAddr;
105
106 /**
107 * True if the register width of the highest implemented exception level is
108 * 64 bits (ARMv8)
109 */
110 bool _highestELIs64;
111
112 /**
113 * Supported physical address range in bits if the highest implemented
114 * exception level is 64 bits (ARMv8)
115 */
116 const uint8_t _physAddrRange64;
117
118 /**
119 * True if ASID is 16 bits in AArch64 (ARMv8)
120 */
121 const bool _haveLargeAsid64;
122
123 /**
124 * Range for memory-mapped m5 pseudo ops. The range will be
125 * invalid/empty if disabled.
126 */
127 const AddrRange _m5opRange;
128
129 /**
130 * True if the Semihosting interface is enabled.
131 */
132 ArmSemihosting *const semihosting;
133
134 protected:
135 /**
136 * Get a boot loader that matches the kernel.
137 *
138 * @param obj Kernel binary
139 * @return Pointer to boot loader ObjectFile or nullptr if there
140 * is no matching boot loader.
141 */
142 ObjectFile *getBootLoader(ObjectFile *const obj);
143
144 public:
145 typedef ArmSystemParams Params;
146 const Params *
147 params() const
148 {
149 return dynamic_cast<const Params *>(_params);
150 }
151
152 ArmSystem(Params *p);
153 ~ArmSystem();
154
155 /**
156 * Initialise the system
157 */
158 virtual void initState();
159
160 virtual Addr fixFuncEventAddr(Addr addr)
161 {
162 // Remove the low bit that thumb symbols have set
163 // but that aren't actually odd aligned
164 if (addr & 0x1)
165 return addr & ~1;
166 return addr;
167 }
168
169 /** true if this a multiprocessor system */
170 bool multiProc;
171
172 /** Returns true if this system implements the Security Extensions */
173 bool haveSecurity() const { return _haveSecurity; }
174
175 /** Returns true if this system implements the Large Physical Address
176 * Extension */
177 bool haveLPAE() const { return _haveLPAE; }
178
179 /** Returns true if this system implements the virtualization
180 * Extensions
181 */
182 bool haveVirtualization() const { return _haveVirtualization; }
183
184 /** Returns true if this system implements the Crypto
185 * Extension
186 */
187 bool haveCrypto() const { return _haveCrypto; }
188
189 /** Sets the pointer to the Generic Timer. */
190 void setGenericTimer(GenericTimer *generic_timer)
191 {
192 _genericTimer = generic_timer;
193 }
194
195 /** Get a pointer to the system's generic timer model */
196 GenericTimer *getGenericTimer() const { return _genericTimer; }
197
198 /** Returns true if the register width of the highest implemented exception
199 * level is 64 bits (ARMv8) */
200 bool highestELIs64() const { return _highestELIs64; }
201
202 /** Returns the highest implemented exception level */
203 ExceptionLevel highestEL() const
204 {
205 if (_haveSecurity)
206 return EL3;
207 if (_haveVirtualization)
208 return EL2;
209 return EL1;
210 }
211
212 /** Returns the reset address if the highest implemented exception level is
213 * 64 bits (ARMv8) */
214 Addr resetAddr() const { return _resetAddr; }
215
216 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
217 bool haveLargeAsid64() const { return _haveLargeAsid64; }
218
219 /** Returns the supported physical address range in bits if the highest
220 * implemented exception level is 64 bits (ARMv8) */
221 uint8_t physAddrRange64() const { return _physAddrRange64; }
222
223 /** Returns the supported physical address range in bits */
224 uint8_t physAddrRange() const
225 {
226 if (_highestELIs64)
227 return _physAddrRange64;
228 if (_haveLPAE)
229 return 40;
230 return 32;
231 }
232
233 /** Returns the physical address mask */
234 Addr physAddrMask() const
235 {
236 return mask(physAddrRange());
237 }
238
239 /**
240 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
241 * an invalid/empty range if disabled.
242 */
243 const AddrRange &m5opRange() const { return _m5opRange; }
244
245 /** Is Arm Semihosting support enabled? */
246 bool haveSemihosting() const { return semihosting != nullptr; }
247
248 /**
249 * Returns a valid ArmSystem pointer if using ARM ISA, it fails
250 * otherwise.
251 */
252 static ArmSystem* getArmSystem(ThreadContext *tc);
253
254 /** Returns true if the system of a specific thread context implements the
255 * Security Extensions
256 */
257 static bool haveSecurity(ThreadContext *tc);
258
259 /** Returns true if the system of a specific thread context implements the
260 * virtualization Extensions
261 */
262 static bool haveVirtualization(ThreadContext *tc);
263
264 /** Returns true if the system of a specific thread context implements the
265 * Large Physical Address Extension
266 */
267 static bool haveLPAE(ThreadContext *tc);
268
269 /** Returns true if the register width of the highest implemented exception
270 * level for the system of a specific thread context is 64 bits (ARMv8)
271 */
272 static bool highestELIs64(ThreadContext *tc);
273
274 /** Returns the highest implemented exception level for the system of a
275 * specific thread context
276 */
277 static ExceptionLevel highestEL(ThreadContext *tc);
278
279 /** Return true if the system implements a specific exception level */
280 static bool haveEL(ThreadContext *tc, ExceptionLevel el);
281
282 /** Returns the reset address if the highest implemented exception level
283 * for the system of a specific thread context is 64 bits (ARMv8)
284 */
285 static Addr resetAddr(ThreadContext *tc);
286
287 /** Returns the supported physical address range in bits for the system of a
288 * specific thread context
289 */
290 static uint8_t physAddrRange(ThreadContext *tc);
291
292 /** Returns the physical address mask for the system of a specific thread
293 * context
294 */
295 static Addr physAddrMask(ThreadContext *tc);
296
297 /** Returns true if ASID is 16 bits for the system of a specific thread
298 * context while in AArch64 (ARMv8) */
299 static bool haveLargeAsid64(ThreadContext *tc);
300
301 /** Is Arm Semihosting support enabled? */
302 static bool haveSemihosting(ThreadContext *tc);
303
304 /** Make a Semihosting call from aarch64 */
305 static uint64_t callSemihosting64(ThreadContext *tc,
306 uint32_t op, uint64_t param);
307
308 /** Make a Semihosting call from aarch32 */
309 static uint32_t callSemihosting32(ThreadContext *tc,
310 uint32_t op, uint32_t param);
311};
312
313class GenericArmSystem : public ArmSystem
314{
315 public:
316 typedef GenericArmSystemParams Params;
317 const Params *
318 params() const
319 {
320 return dynamic_cast<const Params *>(_params);
321 }
322
323 GenericArmSystem(Params *p) : ArmSystem(p) {};
324 virtual ~GenericArmSystem() {};
325
326 /**
327 * Initialise the system
328 */
329 virtual void initState();
330};
331
332#endif
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61 protected:
62 /**
63 * PC based event to skip the dprink() call and emulate its
64 * functionality
65 */
66 Linux::DebugPrintkEvent *debugPrintkEvent;
67
68 /** Bootloaders */
69 std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71 /**
72 * Pointer to the bootloader object
73 */
74 ObjectFile *bootldr;
75
76 /**
77 * True if this system implements the Security Extensions
78 */
79 const bool _haveSecurity;
80
81 /**
82 * True if this system implements the Large Physical Address Extension
83 */
84 const bool _haveLPAE;
85
86 /**
87 * True if this system implements the virtualization Extensions
88 */
89 const bool _haveVirtualization;
90
91 /**
92 * True if this system implements the Crypto Extension
93 */
94 const bool _haveCrypto;
95
96 /**
97 * Pointer to the Generic Timer wrapper.
98 */
99 GenericTimer *_genericTimer;
100
101 /**
102 * Reset address (ARMv8)
103 */
104 const Addr _resetAddr;
105
106 /**
107 * True if the register width of the highest implemented exception level is
108 * 64 bits (ARMv8)
109 */
110 bool _highestELIs64;
111
112 /**
113 * Supported physical address range in bits if the highest implemented
114 * exception level is 64 bits (ARMv8)
115 */
116 const uint8_t _physAddrRange64;
117
118 /**
119 * True if ASID is 16 bits in AArch64 (ARMv8)
120 */
121 const bool _haveLargeAsid64;
122
123 /**
124 * Range for memory-mapped m5 pseudo ops. The range will be
125 * invalid/empty if disabled.
126 */
127 const AddrRange _m5opRange;
128
129 /**
130 * True if the Semihosting interface is enabled.
131 */
132 ArmSemihosting *const semihosting;
133
134 protected:
135 /**
136 * Get a boot loader that matches the kernel.
137 *
138 * @param obj Kernel binary
139 * @return Pointer to boot loader ObjectFile or nullptr if there
140 * is no matching boot loader.
141 */
142 ObjectFile *getBootLoader(ObjectFile *const obj);
143
144 public:
145 typedef ArmSystemParams Params;
146 const Params *
147 params() const
148 {
149 return dynamic_cast<const Params *>(_params);
150 }
151
152 ArmSystem(Params *p);
153 ~ArmSystem();
154
155 /**
156 * Initialise the system
157 */
158 virtual void initState();
159
160 virtual Addr fixFuncEventAddr(Addr addr)
161 {
162 // Remove the low bit that thumb symbols have set
163 // but that aren't actually odd aligned
164 if (addr & 0x1)
165 return addr & ~1;
166 return addr;
167 }
168
169 /** true if this a multiprocessor system */
170 bool multiProc;
171
172 /** Returns true if this system implements the Security Extensions */
173 bool haveSecurity() const { return _haveSecurity; }
174
175 /** Returns true if this system implements the Large Physical Address
176 * Extension */
177 bool haveLPAE() const { return _haveLPAE; }
178
179 /** Returns true if this system implements the virtualization
180 * Extensions
181 */
182 bool haveVirtualization() const { return _haveVirtualization; }
183
184 /** Returns true if this system implements the Crypto
185 * Extension
186 */
187 bool haveCrypto() const { return _haveCrypto; }
188
189 /** Sets the pointer to the Generic Timer. */
190 void setGenericTimer(GenericTimer *generic_timer)
191 {
192 _genericTimer = generic_timer;
193 }
194
195 /** Get a pointer to the system's generic timer model */
196 GenericTimer *getGenericTimer() const { return _genericTimer; }
197
198 /** Returns true if the register width of the highest implemented exception
199 * level is 64 bits (ARMv8) */
200 bool highestELIs64() const { return _highestELIs64; }
201
202 /** Returns the highest implemented exception level */
203 ExceptionLevel highestEL() const
204 {
205 if (_haveSecurity)
206 return EL3;
207 if (_haveVirtualization)
208 return EL2;
209 return EL1;
210 }
211
212 /** Returns the reset address if the highest implemented exception level is
213 * 64 bits (ARMv8) */
214 Addr resetAddr() const { return _resetAddr; }
215
216 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
217 bool haveLargeAsid64() const { return _haveLargeAsid64; }
218
219 /** Returns the supported physical address range in bits if the highest
220 * implemented exception level is 64 bits (ARMv8) */
221 uint8_t physAddrRange64() const { return _physAddrRange64; }
222
223 /** Returns the supported physical address range in bits */
224 uint8_t physAddrRange() const
225 {
226 if (_highestELIs64)
227 return _physAddrRange64;
228 if (_haveLPAE)
229 return 40;
230 return 32;
231 }
232
233 /** Returns the physical address mask */
234 Addr physAddrMask() const
235 {
236 return mask(physAddrRange());
237 }
238
239 /**
240 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
241 * an invalid/empty range if disabled.
242 */
243 const AddrRange &m5opRange() const { return _m5opRange; }
244
245 /** Is Arm Semihosting support enabled? */
246 bool haveSemihosting() const { return semihosting != nullptr; }
247
248 /**
249 * Returns a valid ArmSystem pointer if using ARM ISA, it fails
250 * otherwise.
251 */
252 static ArmSystem* getArmSystem(ThreadContext *tc);
253
254 /** Returns true if the system of a specific thread context implements the
255 * Security Extensions
256 */
257 static bool haveSecurity(ThreadContext *tc);
258
259 /** Returns true if the system of a specific thread context implements the
260 * virtualization Extensions
261 */
262 static bool haveVirtualization(ThreadContext *tc);
263
264 /** Returns true if the system of a specific thread context implements the
265 * Large Physical Address Extension
266 */
267 static bool haveLPAE(ThreadContext *tc);
268
269 /** Returns true if the register width of the highest implemented exception
270 * level for the system of a specific thread context is 64 bits (ARMv8)
271 */
272 static bool highestELIs64(ThreadContext *tc);
273
274 /** Returns the highest implemented exception level for the system of a
275 * specific thread context
276 */
277 static ExceptionLevel highestEL(ThreadContext *tc);
278
279 /** Return true if the system implements a specific exception level */
280 static bool haveEL(ThreadContext *tc, ExceptionLevel el);
281
282 /** Returns the reset address if the highest implemented exception level
283 * for the system of a specific thread context is 64 bits (ARMv8)
284 */
285 static Addr resetAddr(ThreadContext *tc);
286
287 /** Returns the supported physical address range in bits for the system of a
288 * specific thread context
289 */
290 static uint8_t physAddrRange(ThreadContext *tc);
291
292 /** Returns the physical address mask for the system of a specific thread
293 * context
294 */
295 static Addr physAddrMask(ThreadContext *tc);
296
297 /** Returns true if ASID is 16 bits for the system of a specific thread
298 * context while in AArch64 (ARMv8) */
299 static bool haveLargeAsid64(ThreadContext *tc);
300
301 /** Is Arm Semihosting support enabled? */
302 static bool haveSemihosting(ThreadContext *tc);
303
304 /** Make a Semihosting call from aarch64 */
305 static uint64_t callSemihosting64(ThreadContext *tc,
306 uint32_t op, uint64_t param);
307
308 /** Make a Semihosting call from aarch32 */
309 static uint32_t callSemihosting32(ThreadContext *tc,
310 uint32_t op, uint32_t param);
311};
312
313class GenericArmSystem : public ArmSystem
314{
315 public:
316 typedef GenericArmSystemParams Params;
317 const Params *
318 params() const
319 {
320 return dynamic_cast<const Params *>(_params);
321 }
322
323 GenericArmSystem(Params *p) : ArmSystem(p) {};
324 virtual ~GenericArmSystem() {};
325
326 /**
327 * Initialise the system
328 */
329 virtual void initState();
330};
331
332#endif