1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61 protected:
62 /**
63 * PC based event to skip the dprink() call and emulate its
64 * functionality
65 */
66 Linux::DebugPrintkEvent *debugPrintkEvent;
67
68 /** Bootloaders */
69 std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71 /**
72 * Pointer to the bootloader object
73 */
74 ObjectFile *bootldr;
75
76 /**
77 * True if this system implements the Security Extensions
78 */
79 const bool _haveSecurity;
80
81 /**
82 * True if this system implements the Large Physical Address Extension
83 */
84 const bool _haveLPAE;
85
86 /**
87 * True if this system implements the virtualization Extensions
88 */
89 const bool _haveVirtualization;
90
91 /**
92 * True if this system implements the Crypto Extension
93 */
94 const bool _haveCrypto;
95
96 /**
97 * Pointer to the Generic Timer wrapper.
98 */
99 GenericTimer *_genericTimer;
100
101 /**
102 * True if the register width of the highest implemented exception level is
103 * 64 bits (ARMv8)
104 */
105 bool _highestELIs64;
106
107 /**
108 * Reset address if the highest implemented exception level is 64 bits
109 * (ARMv8)
110 */
111 const Addr _resetAddr64;
112
113 /**
114 * Supported physical address range in bits if the highest implemented
115 * exception level is 64 bits (ARMv8)
116 */
117 const uint8_t _physAddrRange64;
118
119 /**
120 * True if ASID is 16 bits in AArch64 (ARMv8)
121 */
122 const bool _haveLargeAsid64;
123
124 /**
125 * Range for memory-mapped m5 pseudo ops. The range will be
126 * invalid/empty if disabled.
127 */
128 const AddrRange _m5opRange;
129
130 /**
131 * True if the Semihosting interface is enabled.
132 */
133 ArmSemihosting *const semihosting;
134
135 protected:
136 /**
137 * Get a boot loader that matches the kernel.
138 *
139 * @param obj Kernel binary
140 * @return Pointer to boot loader ObjectFile or nullptr if there
141 * is no matching boot loader.
142 */
143 ObjectFile *getBootLoader(ObjectFile *const obj);
144
145 public:
146 typedef ArmSystemParams Params;
147 const Params *
148 params() const
149 {
150 return dynamic_cast<const Params *>(_params);
151 }
152
153 ArmSystem(Params *p);
154 ~ArmSystem();
155
156 /**
157 * Initialise the system
158 */
159 virtual void initState();
160
161 virtual Addr fixFuncEventAddr(Addr addr)
162 {
163 // Remove the low bit that thumb symbols have set
164 // but that aren't actually odd aligned
165 if (addr & 0x1)
166 return addr & ~1;
167 return addr;
168 }
169
170 /** true if this a multiprocessor system */
171 bool multiProc;
172
173 /** Returns true if this system implements the Security Extensions */
174 bool haveSecurity() const { return _haveSecurity; }
175
176 /** Returns true if this system implements the Large Physical Address
177 * Extension */
178 bool haveLPAE() const { return _haveLPAE; }
179
180 /** Returns true if this system implements the virtualization
181 * Extensions
182 */
183 bool haveVirtualization() const { return _haveVirtualization; }
184
185 /** Returns true if this system implements the Crypto
186 * Extension
187 */
188 bool haveCrypto() const { return _haveCrypto; }
189
190 /** Sets the pointer to the Generic Timer. */
191 void setGenericTimer(GenericTimer *generic_timer)
192 {
193 _genericTimer = generic_timer;
194 }
195
196 /** Get a pointer to the system's generic timer model */
197 GenericTimer *getGenericTimer() const { return _genericTimer; }
198
199 /** Returns true if the register width of the highest implemented exception
200 * level is 64 bits (ARMv8) */
201 bool highestELIs64() const { return _highestELIs64; }
202
203 /** Returns the highest implemented exception level */
204 ExceptionLevel highestEL() const
205 {
206 if (_haveSecurity)
207 return EL3;
208 if (_haveVirtualization)
209 return EL2;
210 return EL1;
211 }
212
213 /** Returns the reset address if the highest implemented exception level is
214 * 64 bits (ARMv8) */
215 Addr resetAddr64() const { return _resetAddr64; }
216
217 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
218 bool haveLargeAsid64() const { return _haveLargeAsid64; }
219
220 /** Returns the supported physical address range in bits if the highest
221 * implemented exception level is 64 bits (ARMv8) */
222 uint8_t physAddrRange64() const { return _physAddrRange64; }
223
224 /** Returns the supported physical address range in bits */
225 uint8_t physAddrRange() const
226 {
227 if (_highestELIs64)
228 return _physAddrRange64;
229 if (_haveLPAE)
230 return 40;
231 return 32;
232 }
233
234 /** Returns the physical address mask */
235 Addr physAddrMask() const
236 {
237 return mask(physAddrRange());
238 }
239
240 /**
241 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
242 * an invalid/empty range if disabled.
243 */
244 const AddrRange &m5opRange() const { return _m5opRange; }
245
246 /** Is Arm Semihosting support enabled? */
247 bool haveSemihosting() const { return semihosting != nullptr; }
248
249 /**
250 * Returns a valid ArmSystem pointer if using ARM ISA, it fails
251 * otherwise.
252 */
253 static ArmSystem* getArmSystem(ThreadContext *tc);
254
255 /** Returns true if the system of a specific thread context implements the
256 * Security Extensions
257 */
258 static bool haveSecurity(ThreadContext *tc);
259
260 /** Returns true if the system of a specific thread context implements the
261 * virtualization Extensions
262 */
263 static bool haveVirtualization(ThreadContext *tc);
264
265 /** Returns true if the system of a specific thread context implements the
266 * Large Physical Address Extension
267 */
268 static bool haveLPAE(ThreadContext *tc);
269
270 /** Returns true if the register width of the highest implemented exception
271 * level for the system of a specific thread context is 64 bits (ARMv8)
272 */
273 static bool highestELIs64(ThreadContext *tc);
274
275 /** Returns the highest implemented exception level for the system of a
276 * specific thread context
277 */
278 static ExceptionLevel highestEL(ThreadContext *tc);
279
280 /** Return true if the system implements a specific exception level */
281 static bool haveEL(ThreadContext *tc, ExceptionLevel el);
282
283 /** Returns the reset address if the highest implemented exception level
284 * for the system of a specific thread context is 64 bits (ARMv8)
285 */
286 static Addr resetAddr64(ThreadContext *tc);
287
288 /** Returns the supported physical address range in bits for the system of a
289 * specific thread context
290 */
291 static uint8_t physAddrRange(ThreadContext *tc);
292
293 /** Returns the physical address mask for the system of a specific thread
294 * context
295 */
296 static Addr physAddrMask(ThreadContext *tc);
297
298 /** Returns true if ASID is 16 bits for the system of a specific thread
299 * context while in AArch64 (ARMv8) */
300 static bool haveLargeAsid64(ThreadContext *tc);
301
302 /** Is Arm Semihosting support enabled? */
303 static bool haveSemihosting(ThreadContext *tc);
304
305 /** Make a Semihosting call from aarch64 */
306 static uint64_t callSemihosting64(ThreadContext *tc,
307 uint32_t op, uint64_t param);
308
309 /** Make a Semihosting call from aarch32 */
310 static uint32_t callSemihosting32(ThreadContext *tc,
311 uint32_t op, uint32_t param);
312};
313
314class GenericArmSystem : public ArmSystem
315{
316 public:
317 typedef GenericArmSystemParams Params;
318 const Params *
319 params() const
320 {
321 return dynamic_cast<const Params *>(_params);
322 }
323
324 GenericArmSystem(Params *p) : ArmSystem(p) {};
325 virtual ~GenericArmSystem() {};
326
327 /**
328 * Initialise the system
329 */
330 virtual void initState();
331};
332
333#endif
2 * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61 protected:
62 /**
63 * PC based event to skip the dprink() call and emulate its
64 * functionality
65 */
66 Linux::DebugPrintkEvent *debugPrintkEvent;
67
68 /** Bootloaders */
69 std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71 /**
72 * Pointer to the bootloader object
73 */
74 ObjectFile *bootldr;
75
76 /**
77 * True if this system implements the Security Extensions
78 */
79 const bool _haveSecurity;
80
81 /**
82 * True if this system implements the Large Physical Address Extension
83 */
84 const bool _haveLPAE;
85
86 /**
87 * True if this system implements the virtualization Extensions
88 */
89 const bool _haveVirtualization;
90
91 /**
92 * True if this system implements the Crypto Extension
93 */
94 const bool _haveCrypto;
95
96 /**
97 * Pointer to the Generic Timer wrapper.
98 */
99 GenericTimer *_genericTimer;
100
101 /**
102 * True if the register width of the highest implemented exception level is
103 * 64 bits (ARMv8)
104 */
105 bool _highestELIs64;
106
107 /**
108 * Reset address if the highest implemented exception level is 64 bits
109 * (ARMv8)
110 */
111 const Addr _resetAddr64;
112
113 /**
114 * Supported physical address range in bits if the highest implemented
115 * exception level is 64 bits (ARMv8)
116 */
117 const uint8_t _physAddrRange64;
118
119 /**
120 * True if ASID is 16 bits in AArch64 (ARMv8)
121 */
122 const bool _haveLargeAsid64;
123
124 /**
125 * Range for memory-mapped m5 pseudo ops. The range will be
126 * invalid/empty if disabled.
127 */
128 const AddrRange _m5opRange;
129
130 /**
131 * True if the Semihosting interface is enabled.
132 */
133 ArmSemihosting *const semihosting;
134
135 protected:
136 /**
137 * Get a boot loader that matches the kernel.
138 *
139 * @param obj Kernel binary
140 * @return Pointer to boot loader ObjectFile or nullptr if there
141 * is no matching boot loader.
142 */
143 ObjectFile *getBootLoader(ObjectFile *const obj);
144
145 public:
146 typedef ArmSystemParams Params;
147 const Params *
148 params() const
149 {
150 return dynamic_cast<const Params *>(_params);
151 }
152
153 ArmSystem(Params *p);
154 ~ArmSystem();
155
156 /**
157 * Initialise the system
158 */
159 virtual void initState();
160
161 virtual Addr fixFuncEventAddr(Addr addr)
162 {
163 // Remove the low bit that thumb symbols have set
164 // but that aren't actually odd aligned
165 if (addr & 0x1)
166 return addr & ~1;
167 return addr;
168 }
169
170 /** true if this a multiprocessor system */
171 bool multiProc;
172
173 /** Returns true if this system implements the Security Extensions */
174 bool haveSecurity() const { return _haveSecurity; }
175
176 /** Returns true if this system implements the Large Physical Address
177 * Extension */
178 bool haveLPAE() const { return _haveLPAE; }
179
180 /** Returns true if this system implements the virtualization
181 * Extensions
182 */
183 bool haveVirtualization() const { return _haveVirtualization; }
184
185 /** Returns true if this system implements the Crypto
186 * Extension
187 */
188 bool haveCrypto() const { return _haveCrypto; }
189
190 /** Sets the pointer to the Generic Timer. */
191 void setGenericTimer(GenericTimer *generic_timer)
192 {
193 _genericTimer = generic_timer;
194 }
195
196 /** Get a pointer to the system's generic timer model */
197 GenericTimer *getGenericTimer() const { return _genericTimer; }
198
199 /** Returns true if the register width of the highest implemented exception
200 * level is 64 bits (ARMv8) */
201 bool highestELIs64() const { return _highestELIs64; }
202
203 /** Returns the highest implemented exception level */
204 ExceptionLevel highestEL() const
205 {
206 if (_haveSecurity)
207 return EL3;
208 if (_haveVirtualization)
209 return EL2;
210 return EL1;
211 }
212
213 /** Returns the reset address if the highest implemented exception level is
214 * 64 bits (ARMv8) */
215 Addr resetAddr64() const { return _resetAddr64; }
216
217 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
218 bool haveLargeAsid64() const { return _haveLargeAsid64; }
219
220 /** Returns the supported physical address range in bits if the highest
221 * implemented exception level is 64 bits (ARMv8) */
222 uint8_t physAddrRange64() const { return _physAddrRange64; }
223
224 /** Returns the supported physical address range in bits */
225 uint8_t physAddrRange() const
226 {
227 if (_highestELIs64)
228 return _physAddrRange64;
229 if (_haveLPAE)
230 return 40;
231 return 32;
232 }
233
234 /** Returns the physical address mask */
235 Addr physAddrMask() const
236 {
237 return mask(physAddrRange());
238 }
239
240 /**
241 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
242 * an invalid/empty range if disabled.
243 */
244 const AddrRange &m5opRange() const { return _m5opRange; }
245
246 /** Is Arm Semihosting support enabled? */
247 bool haveSemihosting() const { return semihosting != nullptr; }
248
249 /**
250 * Returns a valid ArmSystem pointer if using ARM ISA, it fails
251 * otherwise.
252 */
253 static ArmSystem* getArmSystem(ThreadContext *tc);
254
255 /** Returns true if the system of a specific thread context implements the
256 * Security Extensions
257 */
258 static bool haveSecurity(ThreadContext *tc);
259
260 /** Returns true if the system of a specific thread context implements the
261 * virtualization Extensions
262 */
263 static bool haveVirtualization(ThreadContext *tc);
264
265 /** Returns true if the system of a specific thread context implements the
266 * Large Physical Address Extension
267 */
268 static bool haveLPAE(ThreadContext *tc);
269
270 /** Returns true if the register width of the highest implemented exception
271 * level for the system of a specific thread context is 64 bits (ARMv8)
272 */
273 static bool highestELIs64(ThreadContext *tc);
274
275 /** Returns the highest implemented exception level for the system of a
276 * specific thread context
277 */
278 static ExceptionLevel highestEL(ThreadContext *tc);
279
280 /** Return true if the system implements a specific exception level */
281 static bool haveEL(ThreadContext *tc, ExceptionLevel el);
282
283 /** Returns the reset address if the highest implemented exception level
284 * for the system of a specific thread context is 64 bits (ARMv8)
285 */
286 static Addr resetAddr64(ThreadContext *tc);
287
288 /** Returns the supported physical address range in bits for the system of a
289 * specific thread context
290 */
291 static uint8_t physAddrRange(ThreadContext *tc);
292
293 /** Returns the physical address mask for the system of a specific thread
294 * context
295 */
296 static Addr physAddrMask(ThreadContext *tc);
297
298 /** Returns true if ASID is 16 bits for the system of a specific thread
299 * context while in AArch64 (ARMv8) */
300 static bool haveLargeAsid64(ThreadContext *tc);
301
302 /** Is Arm Semihosting support enabled? */
303 static bool haveSemihosting(ThreadContext *tc);
304
305 /** Make a Semihosting call from aarch64 */
306 static uint64_t callSemihosting64(ThreadContext *tc,
307 uint32_t op, uint64_t param);
308
309 /** Make a Semihosting call from aarch32 */
310 static uint32_t callSemihosting32(ThreadContext *tc,
311 uint32_t op, uint32_t param);
312};
313
314class GenericArmSystem : public ArmSystem
315{
316 public:
317 typedef GenericArmSystemParams Params;
318 const Params *
319 params() const
320 {
321 return dynamic_cast<const Params *>(_params);
322 }
323
324 GenericArmSystem(Params *p) : ArmSystem(p) {};
325 virtual ~GenericArmSystem() {};
326
327 /**
328 * Initialise the system
329 */
330 virtual void initState();
331};
332
333#endif