stage2_mmu.hh (12429:beefb9f5f551) stage2_mmu.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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65 MasterID masterId;
66
67 public:
68 /** This translation class is used to trigger the data fetch once a timing
69 translation returns the translated physical address */
70 class Stage2Translation : public BaseTLB::Translation
71 {
72 private:
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 56 unchanged lines hidden (view full) ---

65 MasterID masterId;
66
67 public:
68 /** This translation class is used to trigger the data fetch once a timing
69 translation returns the translated physical address */
70 class Stage2Translation : public BaseTLB::Translation
71 {
72 private:
73 uint8_t *data;
74 int numBytes;
75 Request req;
76 Event *event;
77 Stage2MMU &parent;
78 Addr oVAddr;
73 uint8_t *data;
74 int numBytes;
75 RequestPtr req;
76 Event *event;
77 Stage2MMU &parent;
78 Addr oVAddr;
79
80 public:
81 Fault fault;
82
83 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
84 Addr _oVAddr);
85
86 void
87 markDelayed() {}
88
89 void
79
80 public:
81 Fault fault;
82
83 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
84 Addr _oVAddr);
85
86 void
87 markDelayed() {}
88
89 void
90 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
90 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
91 BaseTLB::Mode mode);
92
93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
94 {
95 numBytes = size;
91 BaseTLB::Mode mode);
92
93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
94 {
95 numBytes = size;
96 req.setVirt(0, vaddr, size, flags, masterId, 0);
96 req->setVirt(0, vaddr, size, flags, masterId, 0);
97 }
98
99 void translateTiming(ThreadContext *tc)
100 {
97 }
98
99 void translateTiming(ThreadContext *tc)
100 {
101 parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read);
101 parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
102 }
103 };
104
105 typedef ArmStage2MMUParams Params;
106 Stage2MMU(const Params *p);
107
108 /**
109 * Get the port that ultimately belongs to the stage-two MMU, but

--- 21 unchanged lines hidden --- 		102 }
103 };
104
105 typedef ArmStage2MMUParams Params;
106 Stage2MMU(const Params *p);
107
108 /**
109 * Get the port that ultimately belongs to the stage-two MMU, but

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