stage2_mmu.hh (10820:e2a283400c43) stage2_mmu.hh (10873:7c972b9aea16)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "dev/dma_device.hh"
45#include "mem/request.hh"
46#include "params/ArmStage2MMU.hh"
47#include "sim/eventq.hh"
48
49namespace ArmISA {
50
51class Stage2MMU : public SimObject
52{

--- 79 unchanged lines hidden --- 		46#include "mem/request.hh"
47#include "params/ArmStage2MMU.hh"
48#include "sim/eventq.hh"
49
50namespace ArmISA {
51
52class Stage2MMU : public SimObject
53{

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