stage2_mmu.hh (10717:4f8c1bd6fdb8) | stage2_mmu.hh (10820:e2a283400c43) |
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1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 43 unchanged lines hidden (view full) --- 52{ 53 private: 54 TLB *_stage1Tlb; 55 /** The TLB that will cache the stage 2 look ups. */ 56 TLB *_stage2Tlb; 57 58 protected: 59 | 1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 43 unchanged lines hidden (view full) --- 52{ 53 private: 54 TLB *_stage1Tlb; 55 /** The TLB that will cache the stage 2 look ups. */ 56 TLB *_stage2Tlb; 57 58 protected: 59 |
60 /** 61 * A snooping DMA port that currently does nothing besides 62 * extending the DMA port to accept snoops without 63 * complaining. Currently we take no action on any snoops. 64 */ 65 class SnoopingDmaPort : public DmaPort 66 { 67 68 protected: 69 70 virtual void recvTimingSnoopReq(PacketPtr pkt) 71 { } 72 73 virtual Tick recvAtomicSnoop(PacketPtr pkt) 74 { return 0; } 75 76 virtual void recvFunctionalSnoop(PacketPtr pkt) 77 { } 78 79 virtual bool isSnooping() const { return true; } 80 81 public: 82 83 /** 84 * A snooping DMA port merely calls the construtor of the DMA 85 * port. 86 */ 87 SnoopingDmaPort(MemObject *dev, System *s) : 88 DmaPort(dev, s) 89 { } 90 }; 91 | |
92 /** Port to issue translation requests from */ | 60 /** Port to issue translation requests from */ |
93 SnoopingDmaPort port; | 61 DmaPort port; |
94 95 /** Request id for requests generated by this MMU */ 96 MasterID masterId; 97 98 public: 99 /** This translation class is used to trigger the data fetch once a timing 100 translation returns the translated physical address */ 101 class Stage2Translation : public BaseTLB::Translation --- 62 unchanged lines hidden --- | 62 63 /** Request id for requests generated by this MMU */ 64 MasterID masterId; 65 66 public: 67 /** This translation class is used to trigger the data fetch once a timing 68 translation returns the translated physical address */ 69 class Stage2Translation : public BaseTLB::Translation --- 62 unchanged lines hidden --- |