stage2_mmu.hh (10379:c00f6d7e2681) stage2_mmu.hh (10717:4f8c1bd6fdb8)
1/*
1/*
2 * Copyright (c) 2012-2013 ARM Limited
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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50
51class Stage2MMU : public SimObject
52{
53 private:
54 TLB *_stage1Tlb;
55 /** The TLB that will cache the stage 2 look ups. */
56 TLB *_stage2Tlb;
57
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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50
51class Stage2MMU : public SimObject
52{
53 private:
54 TLB *_stage1Tlb;
55 /** The TLB that will cache the stage 2 look ups. */
56 TLB *_stage2Tlb;
57
58 protected:
59
60 /**
61 * A snooping DMA port that currently does nothing besides
62 * extending the DMA port to accept snoops without
63 * complaining. Currently we take no action on any snoops.
64 */
65 class SnoopingDmaPort : public DmaPort
66 {
67
68 protected:
69
70 virtual void recvTimingSnoopReq(PacketPtr pkt)
71 { }
72
73 virtual Tick recvAtomicSnoop(PacketPtr pkt)
74 { return 0; }
75
76 virtual void recvFunctionalSnoop(PacketPtr pkt)
77 { }
78
79 virtual bool isSnooping() const { return true; }
80
81 public:
82
83 /**
84 * A snooping DMA port merely calls the construtor of the DMA
85 * port.
86 */
87 SnoopingDmaPort(MemObject *dev, System *s) :
88 DmaPort(dev, s)
89 { }
90 };
91
92 /** Port to issue translation requests from */
93 SnoopingDmaPort port;
94
95 /** Request id for requests generated by this MMU */
96 MasterID masterId;
97
58 public:
59 /** This translation class is used to trigger the data fetch once a timing
60 translation returns the translated physical address */
61 class Stage2Translation : public BaseTLB::Translation
62 {
63 private:
64 uint8_t *data;
65 int numBytes;

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91 {
92 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
93 }
94 };
95
96 typedef ArmStage2MMUParams Params;
97 Stage2MMU(const Params *p);
98
98 public:
99 /** This translation class is used to trigger the data fetch once a timing
100 translation returns the translated physical address */
101 class Stage2Translation : public BaseTLB::Translation
102 {
103 private:
104 uint8_t *data;
105 int numBytes;

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131 {
132 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
133 }
134 };
135
136 typedef ArmStage2MMUParams Params;
137 Stage2MMU(const Params *p);
138
139 /**
140 * Get the port that ultimately belongs to the stage-two MMU, but
141 * is used by the two table walkers, and is exposed externally and
142 * connected through the stage-one table walker.
143 */
144 DmaPort& getPort() { return port; }
145
146 unsigned int drain(DrainManager *dm);
147
99 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
148 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
100 uint8_t *data, int numBytes, Request::Flags flags, int masterId,
101 bool isFunctional);
149 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
102 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
150 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
103 Stage2Translation *translation, int numBytes, Request::Flags flags,
104 int masterId);
151 Stage2Translation *translation, int numBytes,
152 Request::Flags flags);
105
106 TLB* stage1Tlb() const { return _stage1Tlb; }
107 TLB* stage2Tlb() const { return _stage2Tlb; }
108};
109
110
111
112} // namespace ArmISA
113
114#endif //__ARCH_ARM_STAGE2_MMU_HH__
115
153
154 TLB* stage1Tlb() const { return _stage1Tlb; }
155 TLB* stage2Tlb() const { return _stage2Tlb; }
156};
157
158
159
160} // namespace ArmISA
161
162#endif //__ARCH_ARM_STAGE2_MMU_HH__
163