1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 43 unchanged lines hidden (view full) --- 52{ 53 private: 54 TLB *_stage1Tlb; 55 /** The TLB that will cache the stage 2 look ups. */ 56 TLB *_stage2Tlb; 57 58 protected: 59 |
60 /** Port to issue translation requests from */ |
61 DmaPort port; |
62 63 /** Request id for requests generated by this MMU */ 64 MasterID masterId; 65 66 public: 67 /** This translation class is used to trigger the data fetch once a timing 68 translation returns the translated physical address */ 69 class Stage2Translation : public BaseTLB::Translation --- 62 unchanged lines hidden --- |