73,78c73,78
< uint8_t *data;
< int numBytes;
< Request req;
< Event *event;
< Stage2MMU &parent;
< Addr oVAddr;
---
> uint8_t *data;
> int numBytes;
> RequestPtr req;
> Event *event;
> Stage2MMU &parent;
> Addr oVAddr;
90c90
< finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
---
> finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
96c96
< req.setVirt(0, vaddr, size, flags, masterId, 0);
---
> req->setVirt(0, vaddr, size, flags, masterId, 0);
101c101
< parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read);
---
> parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);