1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "dev/dma_device.hh"
46#include "mem/request.hh"
47#include "params/ArmStage2MMU.hh"
48#include "sim/eventq.hh"
49
50namespace ArmISA {
51
52class Stage2MMU : public SimObject
53{
54 private:
55 TLB *_stage1Tlb;
56 /** The TLB that will cache the stage 2 look ups. */
57 TLB *_stage2Tlb;
58
59 protected:
60
61 /** Port to issue translation requests from */
62 DmaPort port;
63
64 /** Request id for requests generated by this MMU */
65 MasterID masterId;
66
67 public:
68 /** This translation class is used to trigger the data fetch once a timing
69 translation returns the translated physical address */
70 class Stage2Translation : public BaseTLB::Translation
71 {
72 private:
| 1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "dev/dma_device.hh"
46#include "mem/request.hh"
47#include "params/ArmStage2MMU.hh"
48#include "sim/eventq.hh"
49
50namespace ArmISA {
51
52class Stage2MMU : public SimObject
53{
54 private:
55 TLB *_stage1Tlb;
56 /** The TLB that will cache the stage 2 look ups. */
57 TLB *_stage2Tlb;
58
59 protected:
60
61 /** Port to issue translation requests from */
62 DmaPort port;
63
64 /** Request id for requests generated by this MMU */
65 MasterID masterId;
66
67 public:
68 /** This translation class is used to trigger the data fetch once a timing
69 translation returns the translated physical address */
70 class Stage2Translation : public BaseTLB::Translation
71 {
72 private:
|
73 uint8_t *data;
74 int numBytes;
75 Request req;
76 Event *event;
77 Stage2MMU &parent;
78 Addr oVAddr;
| 73 uint8_t *data;
74 int numBytes;
75 RequestPtr req;
76 Event *event;
77 Stage2MMU &parent;
78 Addr oVAddr;
|
79
80 public:
81 Fault fault;
82
83 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
84 Addr _oVAddr);
85
86 void
87 markDelayed() {}
88
89 void
| 79
80 public:
81 Fault fault;
82
83 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
84 Addr _oVAddr);
85
86 void
87 markDelayed() {}
88
89 void
|
90 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
| 90 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
|
91 BaseTLB::Mode mode);
92
93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
94 {
95 numBytes = size;
| 91 BaseTLB::Mode mode);
92
93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
94 {
95 numBytes = size;
|
96 req.setVirt(0, vaddr, size, flags, masterId, 0);
| 96 req->setVirt(0, vaddr, size, flags, masterId, 0);
|
97 }
98
99 void translateTiming(ThreadContext *tc)
100 {
| 97 }
98
99 void translateTiming(ThreadContext *tc)
100 {
|
101 parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read);
| 101 parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
|
102 }
103 };
104
105 typedef ArmStage2MMUParams Params;
106 Stage2MMU(const Params *p);
107
108 /**
109 * Get the port that ultimately belongs to the stage-two MMU, but
110 * is used by the two table walkers, and is exposed externally and
111 * connected through the stage-one table walker.
112 */
113 DmaPort& getPort() { return port; }
114
115 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
116 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
117 void readDataTimed(ThreadContext *tc, Addr descAddr,
118 Stage2Translation *translation, int numBytes,
119 Request::Flags flags);
120
121 TLB* stage1Tlb() const { return _stage1Tlb; }
122 TLB* stage2Tlb() const { return _stage2Tlb; }
123};
124
125
126
127} // namespace ArmISA
128
129#endif //__ARCH_ARM_STAGE2_MMU_HH__
130
| 102 }
103 };
104
105 typedef ArmStage2MMUParams Params;
106 Stage2MMU(const Params *p);
107
108 /**
109 * Get the port that ultimately belongs to the stage-two MMU, but
110 * is used by the two table walkers, and is exposed externally and
111 * connected through the stage-one table walker.
112 */
113 DmaPort& getPort() { return port; }
114
115 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
116 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
117 void readDataTimed(ThreadContext *tc, Addr descAddr,
118 Stage2Translation *translation, int numBytes,
119 Request::Flags flags);
120
121 TLB* stage1Tlb() const { return _stage1Tlb; }
122 TLB* stage2Tlb() const { return _stage2Tlb; }
123};
124
125
126
127} // namespace ArmISA
128
129#endif //__ARCH_ARM_STAGE2_MMU_HH__
130
|