1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/request.hh"
46#include "params/ArmStage2MMU.hh"
47#include "sim/eventq.hh"
48
49namespace ArmISA {
50
51class Stage2MMU : public SimObject
52{
53 private:
54 TLB *_stage1Tlb;
55 /** The TLB that will cache the stage 2 look ups. */
56 TLB *_stage2Tlb;
57
58 protected:
59
| 1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#ifndef __ARCH_ARM_STAGE2_MMU_HH__
41#define __ARCH_ARM_STAGE2_MMU_HH__
42
43#include "arch/arm/faults.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/request.hh"
46#include "params/ArmStage2MMU.hh"
47#include "sim/eventq.hh"
48
49namespace ArmISA {
50
51class Stage2MMU : public SimObject
52{
53 private:
54 TLB *_stage1Tlb;
55 /** The TLB that will cache the stage 2 look ups. */
56 TLB *_stage2Tlb;
57
58 protected:
59
|
94
95 /** Request id for requests generated by this MMU */
96 MasterID masterId;
97
98 public:
99 /** This translation class is used to trigger the data fetch once a timing
100 translation returns the translated physical address */
101 class Stage2Translation : public BaseTLB::Translation
102 {
103 private:
104 uint8_t *data;
105 int numBytes;
106 Request req;
107 Event *event;
108 Stage2MMU &parent;
109 Addr oVAddr;
110
111 public:
112 Fault fault;
113
114 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
115 Addr _oVAddr);
116
117 void
118 markDelayed() {}
119
120 void
121 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
122 BaseTLB::Mode mode);
123
124 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
125 {
126 numBytes = size;
127 req.setVirt(0, vaddr, size, flags, masterId, 0);
128 }
129
130 Fault translateTiming(ThreadContext *tc)
131 {
132 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
133 }
134 };
135
136 typedef ArmStage2MMUParams Params;
137 Stage2MMU(const Params *p);
138
139 /**
140 * Get the port that ultimately belongs to the stage-two MMU, but
141 * is used by the two table walkers, and is exposed externally and
142 * connected through the stage-one table walker.
143 */
144 DmaPort& getPort() { return port; }
145
146 unsigned int drain(DrainManager *dm);
147
148 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
149 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
150 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
151 Stage2Translation *translation, int numBytes,
152 Request::Flags flags);
153
154 TLB* stage1Tlb() const { return _stage1Tlb; }
155 TLB* stage2Tlb() const { return _stage2Tlb; }
156};
157
158
159
160} // namespace ArmISA
161
162#endif //__ARCH_ARM_STAGE2_MMU_HH__
163
| 62
63 /** Request id for requests generated by this MMU */
64 MasterID masterId;
65
66 public:
67 /** This translation class is used to trigger the data fetch once a timing
68 translation returns the translated physical address */
69 class Stage2Translation : public BaseTLB::Translation
70 {
71 private:
72 uint8_t *data;
73 int numBytes;
74 Request req;
75 Event *event;
76 Stage2MMU &parent;
77 Addr oVAddr;
78
79 public:
80 Fault fault;
81
82 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
83 Addr _oVAddr);
84
85 void
86 markDelayed() {}
87
88 void
89 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
90 BaseTLB::Mode mode);
91
92 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
93 {
94 numBytes = size;
95 req.setVirt(0, vaddr, size, flags, masterId, 0);
96 }
97
98 Fault translateTiming(ThreadContext *tc)
99 {
100 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
101 }
102 };
103
104 typedef ArmStage2MMUParams Params;
105 Stage2MMU(const Params *p);
106
107 /**
108 * Get the port that ultimately belongs to the stage-two MMU, but
109 * is used by the two table walkers, and is exposed externally and
110 * connected through the stage-one table walker.
111 */
112 DmaPort& getPort() { return port; }
113
114 unsigned int drain(DrainManager *dm);
115
116 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
117 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
118 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
119 Stage2Translation *translation, int numBytes,
120 Request::Flags flags);
121
122 TLB* stage1Tlb() const { return _stage1Tlb; }
123 TLB* stage2Tlb() const { return _stage2Tlb; }
124};
125
126
127
128} // namespace ArmISA
129
130#endif //__ARCH_ARM_STAGE2_MMU_HH__
131
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