1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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50
51class Stage2MMU : public SimObject
52{
53 private:
54 TLB *_stage1Tlb;
55 /** The TLB that will cache the stage 2 look ups. */
56 TLB *_stage2Tlb;
57
58 public:
59 /** This translation class is used to trigger the data fetch once a timing
60 translation returns the translated physical address */
61 class Stage2Translation : public BaseTLB::Translation
62 {
63 private:
64 uint8_t *data;
65 int numBytes;

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91 {
92 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
93 }
94 };
95
96 typedef ArmStage2MMUParams Params;
97 Stage2MMU(const Params *p);
98
99 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
100 uint8_t *data, int numBytes, Request::Flags flags, int masterId,
101 bool isFunctional);
102 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
103 Stage2Translation *translation, int numBytes, Request::Flags flags,
104 int masterId);
105
106 TLB* stage1Tlb() const { return _stage1Tlb; }
107 TLB* stage2Tlb() const { return _stage2Tlb; }
108};
109
110
111
112} // namespace ArmISA
113
114#endif //__ARCH_ARM_STAGE2_MMU_HH__
115