stage2_mmu.cc (12755:6a5e6dc2824b) stage2_mmu.cc (13795:e21c61d9efb8)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 118 unchanged lines hidden (view full) ---

127 // while doing a translation for a stage 1 page table walk.
128 if (fault != NoFault) {
129 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
130 armFault->annotate(ArmFault::S1PTW, true);
131 armFault->annotate(ArmFault::OVA, oVAddr);
132 }
133
134 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 118 unchanged lines hidden (view full) ---

127 // while doing a translation for a stage 1 page table walk.
128 if (fault != NoFault) {
129 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
130 armFault->annotate(ArmFault::S1PTW, true);
131 armFault->annotate(ArmFault::OVA, oVAddr);
132 }
133
134 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
135 parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
136 event, data, tc->getCpuPtr()->clockPeriod(),
137 req->getFlags());
135 parent.getDMAPort().dmaAction(
136 MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
137 tc->getCpuPtr()->clockPeriod(), req->getFlags());
138 } else {
139 // We can't do the DMA access as there's been a problem, so tell the
140 // event we're done
141 event->process();
142 }
143}
144
145ArmISA::Stage2MMU *
146ArmStage2MMUParams::create()
147{
148 return new ArmISA::Stage2MMU(this);
149}
138 } else {
139 // We can't do the DMA access as there's been a problem, so tell the
140 // event we're done
141 event->process();
142 }
143}
144
145ArmISA::Stage2MMU *
146ArmStage2MMUParams::create()
147{
148 return new ArmISA::Stage2MMU(this);
149}