stage2_mmu.cc (12429:beefb9f5f551) stage2_mmu.cc (12680:91f4d6668b4f)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#include "cpu/base.hh"
47#include "cpu/thread_context.hh"
48
49using namespace ArmISA;
50
51Stage2MMU::Stage2MMU(const Params *p)
52 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
53 port(_stage1Tlb->getTableWalker(), p->sys),
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 37 unchanged lines hidden (view full) ---

46#include "cpu/base.hh"
47#include "cpu/thread_context.hh"
48
49using namespace ArmISA;
50
51Stage2MMU::Stage2MMU(const Params *p)
52 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
53 port(_stage1Tlb->getTableWalker(), p->sys),
54 masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name()))
54 masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
55{
56 // we use the stage-one table walker as the parent of the port,
57 // and to get our master id, this is done to keep things
58 // symmetrical with other ISAs in terms of naming and stats
59 stage1Tlb()->setMMU(this, masterId);
60 stage2Tlb()->setMMU(this, masterId);
61}
62

--- 85 unchanged lines hidden --- 		55{
56 // we use the stage-one table walker as the parent of the port,
57 // and to get our master id, this is done to keep things
58 // symmetrical with other ISAs in terms of naming and stats
59 stage1Tlb()->setMMU(this, masterId);
60 stage2Tlb()->setMMU(this, masterId);
61}
62

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