stage2_mmu.cc (10537:47fe87b0cf97) | stage2_mmu.cc (10717:4f8c1bd6fdb8) |
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1/* | 1/* |
2 * Copyright (c) 2012-2013 ARM Limited | 2 * Copyright (c) 2012-2013, 2015 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 21 unchanged lines hidden (view full) --- 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grocutt 38 */ 39 | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 21 unchanged lines hidden (view full) --- 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grocutt 38 */ 39 |
40#include "arch/arm/faults.hh" | |
41#include "arch/arm/stage2_mmu.hh" | 40#include "arch/arm/stage2_mmu.hh" |
41#include "arch/arm/faults.hh" |
|
42#include "arch/arm/system.hh" | 42#include "arch/arm/system.hh" |
43#include "arch/arm/table_walker.hh" |
|
43#include "arch/arm/tlb.hh" 44#include "cpu/base.hh" 45#include "cpu/thread_context.hh" | 44#include "arch/arm/tlb.hh" 45#include "cpu/base.hh" 46#include "cpu/thread_context.hh" |
46#include "debug/Checkpoint.hh" 47#include "debug/TLB.hh" 48#include "debug/TLBVerbose.hh" | |
49 50using namespace ArmISA; 51 52Stage2MMU::Stage2MMU(const Params *p) | 47 48using namespace ArmISA; 49 50Stage2MMU::Stage2MMU(const Params *p) |
53 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb) | 51 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), 52 port(_stage1Tlb->getTableWalker(), p->sys), 53 masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) |
54{ | 54{ |
55 stage1Tlb()->setMMU(this); 56 stage2Tlb()->setMMU(this); | 55 // we use the stage-one table walker as the parent of the port, 56 // and to get our master id, this is done to keep things 57 // symmetrical with other ISAs in terms of naming and stats 58 stage1Tlb()->setMMU(this, masterId); 59 stage2Tlb()->setMMU(this, masterId); |
57} 58 59Fault 60Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, | 60} 61 62Fault 63Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, |
61 uint8_t *data, int numBytes, Request::Flags flags, int masterId, 62 bool isFunctional) | 64 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional) |
63{ 64 Fault fault; 65 66 // translate to physical address using the second stage MMU 67 Request req = Request(); 68 req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 69 if (isFunctional) { 70 fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read); 71 } else { 72 fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read); 73 } 74 75 // Now do the access. 76 if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) { 77 Packet pkt = Packet(&req, MemCmd::ReadReq); 78 pkt.dataStatic(data); 79 if (isFunctional) { | 65{ 66 Fault fault; 67 68 // translate to physical address using the second stage MMU 69 Request req = Request(); 70 req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 71 if (isFunctional) { 72 fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read); 73 } else { 74 fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read); 75 } 76 77 // Now do the access. 78 if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) { 79 Packet pkt = Packet(&req, MemCmd::ReadReq); 80 pkt.dataStatic(data); 81 if (isFunctional) { |
80 stage1Tlb()->getWalkerPort().sendFunctional(&pkt); | 82 port.sendFunctional(&pkt); |
81 } else { | 83 } else { |
82 stage1Tlb()->getWalkerPort().sendAtomic(&pkt); | 84 port.sendAtomic(&pkt); |
83 } 84 assert(!pkt.isError()); 85 } 86 87 // If there was a fault annotate it with the flag saying the foult occured 88 // while doing a translation for a stage 1 page table walk. 89 if (fault != NoFault) { 90 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 91 armFault->annotate(ArmFault::S1PTW, true); 92 armFault->annotate(ArmFault::OVA, oVAddr); 93 } 94 return fault; 95} 96 97Fault 98Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, | 85 } 86 assert(!pkt.isError()); 87 } 88 89 // If there was a fault annotate it with the flag saying the foult occured 90 // while doing a translation for a stage 1 page table walk. 91 if (fault != NoFault) { 92 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 93 armFault->annotate(ArmFault::S1PTW, true); 94 armFault->annotate(ArmFault::OVA, oVAddr); 95 } 96 return fault; 97} 98 99Fault 100Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, |
99 Stage2Translation *translation, int numBytes, Request::Flags flags, 100 int masterId) | 101 Stage2Translation *translation, int numBytes, 102 Request::Flags flags) |
101{ 102 Fault fault; 103 // translate to physical address using the second stage MMU 104 translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId); 105 fault = translation->translateTiming(tc); 106 return fault; 107} 108 --- 14 unchanged lines hidden (view full) --- 123 // while doing a translation for a stage 1 page table walk. 124 if (fault != NoFault) { 125 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 126 armFault->annotate(ArmFault::S1PTW, true); 127 armFault->annotate(ArmFault::OVA, oVAddr); 128 } 129 130 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { | 103{ 104 Fault fault; 105 // translate to physical address using the second stage MMU 106 translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId); 107 fault = translation->translateTiming(tc); 108 return fault; 109} 110 --- 14 unchanged lines hidden (view full) --- 125 // while doing a translation for a stage 1 page table walk. 126 if (fault != NoFault) { 127 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 128 armFault->annotate(ArmFault::S1PTW, true); 129 armFault->annotate(ArmFault::OVA, oVAddr); 130 } 131 132 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { |
131 DmaPort& port = parent.stage1Tlb()->getWalkerPort(); 132 port.dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes, 133 event, data, tc->getCpuPtr()->clockPeriod(), 134 req->getFlags()); | 133 parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes, 134 event, data, tc->getCpuPtr()->clockPeriod(), 135 req->getFlags()); |
135 } else { 136 // We can't do the DMA access as there's been a problem, so tell the 137 // event we're done 138 event->process(); 139 } 140} 141 | 136 } else { 137 // We can't do the DMA access as there's been a problem, so tell the 138 // event we're done 139 event->process(); 140 } 141} 142 |
143unsigned int 144Stage2MMU::drain(DrainManager *dm) 145{ 146 return port.drain(dm); 147} 148 |
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142ArmISA::Stage2MMU * 143ArmStage2MMUParams::create() 144{ 145 return new ArmISA::Stage2MMU(this); 146} | 149ArmISA::Stage2MMU * 150ArmStage2MMUParams::create() 151{ 152 return new ArmISA::Stage2MMU(this); 153} |