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< * Copyright (c) 2012-2013 ARM Limited
---
> * Copyright (c) 2012-2013, 2015 ARM Limited
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< #include "arch/arm/faults.hh"
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> #include "arch/arm/faults.hh"
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> #include "arch/arm/table_walker.hh"
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< #include "debug/Checkpoint.hh"
< #include "debug/TLB.hh"
< #include "debug/TLBVerbose.hh"
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< : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb)
---
> : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
> port(_stage1Tlb->getTableWalker(), p->sys),
> masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name()))
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< stage1Tlb()->setMMU(this);
< stage2Tlb()->setMMU(this);
---
> // we use the stage-one table walker as the parent of the port,
> // and to get our master id, this is done to keep things
> // symmetrical with other ISAs in terms of naming and stats
> stage1Tlb()->setMMU(this, masterId);
> stage2Tlb()->setMMU(this, masterId);
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< uint8_t *data, int numBytes, Request::Flags flags, int masterId,
< bool isFunctional)
---
> uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional)
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< stage1Tlb()->getWalkerPort().sendFunctional(&pkt);
---
> port.sendFunctional(&pkt);
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< stage1Tlb()->getWalkerPort().sendAtomic(&pkt);
---
> port.sendAtomic(&pkt);
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< Stage2Translation *translation, int numBytes, Request::Flags flags,
< int masterId)
---
> Stage2Translation *translation, int numBytes,
> Request::Flags flags)
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< DmaPort& port = parent.stage1Tlb()->getWalkerPort();
< port.dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
< event, data, tc->getCpuPtr()->clockPeriod(),
< req->getFlags());
---
> parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
> event, data, tc->getCpuPtr()->clockPeriod(),
> req->getFlags());
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> unsigned int
> Stage2MMU::drain(DrainManager *dm)
> {
> return port.drain(dm);
> }
>