stage2_lookup.cc (12736:1604f2c8ec5e) stage2_lookup.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 43 unchanged lines hidden (view full) ---

52#include "sim/system.hh"
53
54using namespace ArmISA;
55
56Fault
57Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
58
59{
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 43 unchanged lines hidden (view full) ---

52#include "sim/system.hh"
53
54using namespace ArmISA;
55
56Fault
57Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
58
59{
60 fault = stage2Tlb->getTE(&stage2Te, &req, tc, mode, this, timing,
60 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
61 functional, false, tranType);
62 // Call finish if we're done already
63 if ((fault != NoFault) || (stage2Te != NULL)) {
64 // Since we directly requested the table entry (which we need later on
65 // to merge the attributes) then we've skipped some stage2 permissions
66 // checking. So call translate on stage 2 to do the checking. As the
67 // entry is now in the TLB this should always hit the cache.
68 if (fault == NoFault) {
69 if (ELIs64(tc, EL2))
61 functional, false, tranType);
62 // Call finish if we're done already
63 if ((fault != NoFault) || (stage2Te != NULL)) {
64 // Since we directly requested the table entry (which we need later on
65 // to merge the attributes) then we've skipped some stage2 permissions
66 // checking. So call translate on stage 2 to do the checking. As the
67 // entry is now in the TLB this should always hit the cache.
68 if (fault == NoFault) {
69 if (ELIs64(tc, EL2))
70 fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc);
70 fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc);
71 else
71 else
72 fault = stage2Tlb->checkPermissions(stage2Te, &req, mode);
72 fault = stage2Tlb->checkPermissions(stage2Te, req, mode);
73 }
74
73 }
74
75 mergeTe(&req, mode);
75 mergeTe(req, mode);
76 *destTe = stage1Te;
77 }
78 return fault;
79}
80
81void
76 *destTe = stage1Te;
77 }
78 return fault;
79}
80
81void
82Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
82Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
83{
84 // Check again that we haven't got a fault
85 if (fault == NoFault) {
86 assert(stage2Te != NULL);
87
88 // Now we have the table entries for both stages of translation
89 // merge them and insert the result into the stage 1 TLB. See
90 // CombineS1S2Desc() in pseudocode

--- 80 unchanged lines hidden (view full) ---

171 // details of the original stage 1 virtual address
172 reinterpret_cast<ArmFault *>(fault.get())->annotate(ArmFault::OVA,
173 s1Req->getVaddr());
174 }
175 complete = true;
176}
177
178void
83{
84 // Check again that we haven't got a fault
85 if (fault == NoFault) {
86 assert(stage2Te != NULL);
87
88 // Now we have the table entries for both stages of translation
89 // merge them and insert the result into the stage 1 TLB. See
90 // CombineS1S2Desc() in pseudocode

--- 80 unchanged lines hidden (view full) ---

171 // details of the original stage 1 virtual address
172 reinterpret_cast<ArmFault *>(fault.get())->annotate(ArmFault::OVA,
173 s1Req->getVaddr());
174 }
175 complete = true;
176}
177
178void
179Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
179Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req,
180 ThreadContext *tc, BaseTLB::Mode mode)
181{
182 fault = _fault;
183 // if we haven't got the table entry get it now
184 if ((fault == NoFault) && (stage2Te == NULL)) {
185 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
186 timing, functional, false, tranType);
187 }

--- 18 unchanged lines hidden --- 		180 ThreadContext *tc, BaseTLB::Mode mode)
181{
182 fault = _fault;
183 // if we haven't got the table entry get it now
184 if ((fault == NoFault) && (stage2Te == NULL)) {
185 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
186 timing, functional, false, tranType);
187 }

--- 18 unchanged lines hidden ---