1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 * Giacomo Gabrielli
39 */
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/stage2_lookup.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/table_walker.hh"
45#include "arch/arm/tlb.hh"
46#include "cpu/base.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Checkpoint.hh"
49#include "debug/TLB.hh"
50#include "debug/TLBVerbose.hh"
51#include "sim/system.hh"
52
53using namespace ArmISA;
54
55Fault
56Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
57
58{
59 fault = stage2Tlb->getTE(&stage2Te, &req, tc, mode, this, timing,
60 functional, false, tranType);
61 // Call finish if we're done already
62 if ((fault != NoFault) || (stage2Te != NULL)) {
63 // Since we directly requested the table entry (which we need later on
64 // to merge the attributes) then we've skipped some stage2 permissions
65 // checking. So call translate on stage 2 to do the checking. As the
66 // entry is now in the TLB this should always hit the cache.
67 if (fault == NoFault) {
68 if (inAArch64(tc))
69 fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc);
70 else
71 fault = stage2Tlb->checkPermissions(stage2Te, &req, mode);
72 }
73
74 mergeTe(&req, mode);
75 *destTe = stage1Te;
76 }
77 return fault;
78}
79
80void
81Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
82{
83 // Check again that we haven't got a fault
84 if (fault == NoFault) {
85 assert(stage2Te != NULL);
86
87 // Now we have the table entries for both stages of translation
88 // merge them and insert the result into the stage 1 TLB. See
89 // CombineS1S2Desc() in pseudocode
90 stage1Te.N = stage2Te->N;
91 stage1Te.nonCacheable |= stage2Te->nonCacheable;
92 stage1Te.xn |= stage2Te->xn;
93
94 if (stage1Te.size > stage2Te->size) {
95 // Size mismatch also implies vpn mismatch (this is shifted by
96 // sizebits!).
97 stage1Te.vpn = s1Req->getVaddr() / (stage2Te->size+1);
98 stage1Te.pfn = stage2Te->pfn;
99 stage1Te.size = stage2Te->size;
100 } else if (stage1Te.size < stage2Te->size) {
101 // Guest 4K could well be section-backed by host hugepage! In this
102 // case a 4K entry is added but pfn needs to be adjusted. New PFN =
103 // offset into section PFN given by stage2 IPA treated as a stage1
104 // page size.
105 stage1Te.pfn = (stage2Te->pfn * ((stage2Te->size+1) / (stage1Te.size+1))) +
106 (stage2Te->vpn / (stage1Te.size+1));
107 // Size remains smaller of the two.
108 } else {
109 // Matching sizes
110 stage1Te.pfn = stage2Te->pfn;
111 }
112
113 if (stage2Te->mtype == TlbEntry::MemoryType::StronglyOrdered ||
114 stage1Te.mtype == TlbEntry::MemoryType::StronglyOrdered) {
115 stage1Te.mtype = TlbEntry::MemoryType::StronglyOrdered;
116 } else if (stage2Te->mtype == TlbEntry::MemoryType::Device ||
117 stage1Te.mtype == TlbEntry::MemoryType::Device) {
118 stage1Te.mtype = TlbEntry::MemoryType::Device;
119 } else {
120 stage1Te.mtype = TlbEntry::MemoryType::Normal;
121 }
122
123 if (stage1Te.mtype == TlbEntry::MemoryType::Normal) {
124
125 if (stage2Te->innerAttrs == 0 ||
126 stage1Te.innerAttrs == 0) {
127 // either encoding Non-cacheable
128 stage1Te.innerAttrs = 0;
129 } else if (stage2Te->innerAttrs == 2 ||
130 stage1Te.innerAttrs == 2) {
131 // either encoding Write-Through cacheable
132 stage1Te.innerAttrs = 2;
133 } else {
134 // both encodings Write-Back
135 stage1Te.innerAttrs = 3;
136 }
137
138 if (stage2Te->outerAttrs == 0 ||
139 stage1Te.outerAttrs == 0) {
140 // either encoding Non-cacheable
141 stage1Te.outerAttrs = 0;
142 } else if (stage2Te->outerAttrs == 2 ||
143 stage1Te.outerAttrs == 2) {
144 // either encoding Write-Through cacheable
145 stage1Te.outerAttrs = 2;
146 } else {
147 // both encodings Write-Back
148 stage1Te.outerAttrs = 3;
149 }
150
151 stage1Te.shareable |= stage2Te->shareable;
152 stage1Te.outerShareable |= stage2Te->outerShareable;
153 if (stage1Te.innerAttrs == 0 &&
154 stage1Te.outerAttrs == 0) {
155 // something Non-cacheable at each level is outer shareable
156 stage1Te.shareable = true;
157 stage1Te.outerShareable = true;
158 }
159 } else {
160 stage1Te.shareable = true;
161 stage1Te.outerShareable = true;
162 }
163 stage1Te.updateAttributes();
164 }
165
166 // if there's a fault annotate it,
167 if (fault != NoFault) {
168 // If the second stage of translation generated a fault add the
169 // details of the original stage 1 virtual address
170 reinterpret_cast<ArmFault *>(fault.get())->annotate(ArmFault::OVA,
171 s1Req->getVaddr());
172 }
173 complete = true;
174}
175
176void
177Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
178 ThreadContext *tc, BaseTLB::Mode mode)
179{
180 fault = _fault;
181 // if we haven't got the table entry get it now
182 if ((fault == NoFault) && (stage2Te == NULL)) {
183 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
184 timing, functional, false, tranType);
185 }
186
187 // Now we have the stage 2 table entry we need to merge it with the stage
188 // 1 entry we were given at the start
189 mergeTe(req, mode);
190
191 if (fault != NoFault) {
192 transState->finish(fault, req, tc, mode);
193 } else if (timing) {
194 // Now notify the original stage 1 translation that we finally have
195 // a result
196 stage1Tlb->translateComplete(s1Req, tc, transState, mode, tranType, true);
197 }
198 // if we have been asked to delete ourselfs do it now
199 if (selfDelete) {
200 delete this;
201 }
202}
203