remote_gdb.cc (9374:227a38f9d98c) remote_gdb.cc (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010, 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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133#include <unistd.h>
134
135#include <string>
136
137#include "arch/arm/decoder.hh"
138#include "arch/arm/pagetable.hh"
139#include "arch/arm/registers.hh"
140#include "arch/arm/remote_gdb.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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133#include <unistd.h>
134
135#include <string>
136
137#include "arch/arm/decoder.hh"
138#include "arch/arm/pagetable.hh"
139#include "arch/arm/registers.hh"
140#include "arch/arm/remote_gdb.hh"
141#include "arch/arm/system.hh"
141#include "arch/arm/utility.hh"
142#include "arch/arm/vtophys.hh"
143#include "base/intmath.hh"
144#include "base/remote_gdb.hh"
145#include "base/socket.hh"
146#include "base/trace.hh"
147#include "cpu/static_inst.hh"
148#include "cpu/thread_context.hh"

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154#include "mem/port.hh"
155#include "sim/full_system.hh"
156#include "sim/system.hh"
157
158using namespace std;
159using namespace ArmISA;
160
161RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
142#include "arch/arm/utility.hh"
143#include "arch/arm/vtophys.hh"
144#include "base/intmath.hh"
145#include "base/remote_gdb.hh"
146#include "base/socket.hh"
147#include "base/trace.hh"
148#include "cpu/static_inst.hh"
149#include "cpu/thread_context.hh"

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155#include "mem/port.hh"
156#include "sim/full_system.hh"
157#include "sim/system.hh"
158
159using namespace std;
160using namespace ArmISA;
161
162RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
162 : BaseRemoteGDB(_system, tc, NUMREGS)
163 : BaseRemoteGDB(_system, tc, MAX_NUMREGS)
163{
164}
165
166/*
167 * Determine if the mapping at va..(va+len) is valid.
168 */
169bool
170RemoteGDB::acc(Addr va, size_t len)

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199 */
200void
201RemoteGDB::getregs()
202{
203 DPRINTF(GDBAcc, "getregs in remotegdb \n");
204
205 memset(gdbregs.regs, 0, gdbregs.bytes());
206
164{
165}
166
167/*
168 * Determine if the mapping at va..(va+len) is valid.
169 */
170bool
171RemoteGDB::acc(Addr va, size_t len)

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200 */
201void
202RemoteGDB::getregs()
203{
204 DPRINTF(GDBAcc, "getregs in remotegdb \n");
205
206 memset(gdbregs.regs, 0, gdbregs.bytes());
207
207 // R0-R15 supervisor mode
208 // arm registers are 32 bits wide, gdb registers are 64 bits wide
209 // two arm registers are packed into one gdb register (little endian)
210 gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 |
211 context->readIntReg(INTREG_R0);
212 gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 |
213 context->readIntReg(INTREG_R2);
214 gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 |
215 context->readIntReg(INTREG_R4);
216 gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 |
217 context->readIntReg(INTREG_R6);
218 gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 |
219 context->readIntReg(INTREG_R8);
220 gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32|
221 context->readIntReg(INTREG_R10);
222 gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 |
223 context->readIntReg(INTREG_R12);
224 gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 |
225 context->readIntReg(INTREG_LR);
208 if (inAArch64(context)) { // AArch64
209 // x0-x31
210 for (int i = 0; i < 32; ++i) {
211 gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i);
212 }
213 // pc
214 gdbregs.regs[REG_PC_64] = context->pcState().pc();
215 // cpsr
216 gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR);
217 // v0-v31
218 for (int i = 0; i < 32; ++i) {
219 gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>(
220 context->readFloatRegBits(i * 4 + 3)) << 32 |
221 context->readFloatRegBits(i * 4 + 2);
222 gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>(
223 context->readFloatRegBits(i * 4 + 1)) << 32 |
224 context->readFloatRegBits(i * 4 + 0);
225 }
226 } else { // AArch32
227 // R0-R15 supervisor mode
228 // arm registers are 32 bits wide, gdb registers are 64 bits wide two
229 // arm registers are packed into one gdb register (little endian)
230 gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 |
231 context->readIntReg(INTREG_R0);
232 gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 |
233 context->readIntReg(INTREG_R2);
234 gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 |
235 context->readIntReg(INTREG_R4);
236 gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 |
237 context->readIntReg(INTREG_R6);
238 gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 |
239 context->readIntReg(INTREG_R8);
240 gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32|
241 context->readIntReg(INTREG_R10);
242 gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 |
243 context->readIntReg(INTREG_R12);
244 gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 |
245 context->readIntReg(INTREG_LR);
226
246
227 // CPSR
228 gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
247 // CPSR
248 gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
229
249
230 // vfpv3/neon floating point registers (32 double or 64 float)
250 // vfpv3/neon floating point registers (32 double or 64 float)
231
251
232 gdbregs.regs[REG_F0] =
233 static_cast(context->readFloatRegBits(0)) << 32 |
234 gdbregs.regs[REG_CPSR];
252 gdbregs.regs[REG_F0] =
253 static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 |
254 gdbregs.regs[REG_CPSR];
235
255
236 for (int i = 1; i < (NumFloatArchRegs>>1); ++i) {
237 gdbregs.regs[i + REG_F0] =
238 static_cast(context->readFloatRegBits(2*i)) << 32 |
239 context->readFloatRegBits(2*i-1);
240 }
256 for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) {
257 gdbregs.regs[i + REG_F0] =
258 static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 |
259 context->readFloatRegBits(2*i-1);
260 }
241
261
242 // FPSCR
243 gdbregs.regs[REG_FPSCR] =
244 static_cast<uint64_t>(context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 |
245 context->readFloatRegBits(NumFloatArchRegs - 1);
262 // FPSCR
263 gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>(
264 context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 |
265 context->readFloatRegBits(NumFloatV7ArchRegs - 1);
266 }
246}
247
248/*
249 * Translate the GDB register format into the kernel debugger register
250 * format.
251 */
252void
253RemoteGDB::setregs()
254{
255
256 DPRINTF(GDBAcc, "setregs in remotegdb \n");
267}
268
269/*
270 * Translate the GDB register format into the kernel debugger register
271 * format.
272 */
273void
274RemoteGDB::setregs()
275{
276
277 DPRINTF(GDBAcc, "setregs in remotegdb \n");
278 if (inAArch64(context)) { // AArch64
279 // x0-x31
280 for (int i = 0; i < 32; ++i) {
281 context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]);
282 }
283 // pc
284 context->pcState(gdbregs.regs[REG_PC_64]);
285 // cpsr
286 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]);
287 // v0-v31
288 for (int i = 0; i < 32; ++i) {
289 context->setFloatRegBits(i * 4 + 3,
290 gdbregs.regs[REG_V0 + 2 * i] >> 32);
291 context->setFloatRegBits(i * 4 + 2,
292 gdbregs.regs[REG_V0 + 2 * i]);
293 context->setFloatRegBits(i * 4 + 1,
294 gdbregs.regs[REG_V0 + 2 * i + 1] >> 32);
295 context->setFloatRegBits(i * 4 + 0,
296 gdbregs.regs[REG_V0 + 2 * i + 1]);
297 }
298 } else { // AArch32
299 // R0-R15 supervisor mode
300 // arm registers are 32 bits wide, gdb registers are 64 bits wide
301 // two arm registers are packed into one gdb register (little endian)
302 context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0));
303 context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32));
304 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0));
305 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32));
306 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0));
307 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32));
308 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0));
309 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32));
310 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0));
311 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32));
312 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0));
313 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32));
314 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0));
315 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32));
316 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0));
317 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32));
257
318
258 // R0-R15 supervisor mode
259 // arm registers are 32 bits wide, gdb registers are 64 bits wide
260 // two arm registers are packed into one gdb register (little endian)
261 context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0));
262 context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32));
263 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0));
264 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32));
265 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0));
266 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32));
267 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0));
268 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32));
269 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0));
270 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32));
271 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0));
272 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32));
273 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0));
274 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32));
275 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0));
276 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32));
319 //CPSR
320 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]);
277
321
278 //CPSR
279 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]);
322 //vfpv3/neon floating point registers (32 double or 64 float)
323 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32);
280
324
281 //vfpv3/neon floating point registers (32 double or 64 float)
282 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32);
325 for (int i = 1; i < NumFloatV7ArchRegs; ++i) {
326 if (i%2) {
327 int j = (i+1)/2;
328 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0));
329 } else {
330 int j = i/2;
331 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32);
332 }
333 }
283
334
284 for (int i = 1; i < NumFloatArchRegs; ++i) {
285 if(i%2){
286 int j = (i+1)/2;
287 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0));
288 }
289 else{
290 int j = i/2;
291 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32);
292 }
335 //FPSCR
336 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
293 }
337 }
294
295 //FPSCR
296 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
297}
298
299void
300RemoteGDB::clearSingleStep()
301{
302 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
303 takenBkpt, notTakenBkpt);
304

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339
340void
341RemoteGDB::clearSingleStep()
342{
343 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
344 takenBkpt, notTakenBkpt);
345

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