remote_gdb.cc (13579:c892d017124f) remote_gdb.cc (14238:f5d137fd3a75)
1/*
2 * Copyright 2015 LabWare
3 * Copyright 2014 Google Inc.
1/*
2 * Copyright 2015 LabWare
3 * Copyright 2014 Google Inc.
4 * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited
4 * Copyright (c) 2010, 2013, 2016, 2018-2019 ARM Limited
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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207 r.x[i] = context->readIntReg(INTREG_X0 + i);
208 r.spx = context->readIntReg(INTREG_SPX);
209 r.pc = context->pcState().pc();
210 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
211
212 size_t base = 0;
213 for (int i = 0; i < NumVecV8ArchRegs; i++) {
214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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207 r.x[i] = context->readIntReg(INTREG_X0 + i);
208 r.spx = context->readIntReg(INTREG_SPX);
209 r.pc = context->pcState().pc();
210 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
211
212 size_t base = 0;
213 for (int i = 0; i < NumVecV8ArchRegs; i++) {
214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
215 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
215 for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
216 r.v[base] = v[j];
217 base++;
218 }
219 }
220 r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR);
221 r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR);
222}
223

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236 // updating CPSR/PSTATE since that might affect how SPX gets
237 // mapped.
238 context->setIntReg(INTREG_SPX, r.spx);
239
240 size_t base = 0;
241 for (int i = 0; i < NumVecV8ArchRegs; i++) {
242 auto v = (context->getWritableVecReg(
243 RegId(VecRegClass, i))).as<VecElem>();
216 r.v[base] = v[j];
217 base++;
218 }
219 }
220 r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR);
221 r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR);
222}
223

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236 // updating CPSR/PSTATE since that might affect how SPX gets
237 // mapped.
238 context->setIntReg(INTREG_SPX, r.spx);
239
240 size_t base = 0;
241 for (int i = 0; i < NumVecV8ArchRegs; i++) {
242 auto v = (context->getWritableVecReg(
243 RegId(VecRegClass, i))).as<VecElem>();
244 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
244 for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
245 v[j] = r.v[base];
246 base++;
247 }
248 }
249 context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
250 context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
251}
252

--- 93 unchanged lines hidden --- 		245 v[j] = r.v[base];
246 base++;
247 }
248 }
249 context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
250 context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
251}
252

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