remote_gdb.cc (13471:f41c4625aa79) remote_gdb.cc (13579:c892d017124f)
1/*
2 * Copyright 2015 LabWare
3 * Copyright 2014 Google Inc.
1/*
2 * Copyright 2015 LabWare
3 * Copyright 2014 Google Inc.
4 * Copyright (c) 2010, 2013, 2016 ARM Limited
4 * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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145#include "arch/arm/system.hh"
146#include "arch/arm/utility.hh"
147#include "arch/arm/vtophys.hh"
148#include "base/chunk_generator.hh"
149#include "base/intmath.hh"
150#include "base/remote_gdb.hh"
151#include "base/socket.hh"
152#include "base/trace.hh"
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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145#include "arch/arm/system.hh"
146#include "arch/arm/utility.hh"
147#include "arch/arm/vtophys.hh"
148#include "base/chunk_generator.hh"
149#include "base/intmath.hh"
150#include "base/remote_gdb.hh"
151#include "base/socket.hh"
152#include "base/trace.hh"
153#include "blobs/gdb_xml_aarch64_core.hh"
154#include "blobs/gdb_xml_aarch64_fpu.hh"
155#include "blobs/gdb_xml_aarch64_target.hh"
156#include "blobs/gdb_xml_arm_core.hh"
157#include "blobs/gdb_xml_arm_target.hh"
158#include "blobs/gdb_xml_arm_vfpv3.hh"
153#include "cpu/static_inst.hh"
154#include "cpu/thread_context.hh"
155#include "cpu/thread_state.hh"
156#include "debug/GDBAcc.hh"
157#include "debug/GDBMisc.hh"
158#include "mem/page_table.hh"
159#include "mem/physical.hh"
160#include "mem/port.hh"

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206 size_t base = 0;
207 for (int i = 0; i < NumVecV8ArchRegs; i++) {
208 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
209 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
210 r.v[base] = v[j];
211 base++;
212 }
213 }
159#include "cpu/static_inst.hh"
160#include "cpu/thread_context.hh"
161#include "cpu/thread_state.hh"
162#include "debug/GDBAcc.hh"
163#include "debug/GDBMisc.hh"
164#include "mem/page_table.hh"
165#include "mem/physical.hh"
166#include "mem/port.hh"

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212 size_t base = 0;
213 for (int i = 0; i < NumVecV8ArchRegs; i++) {
214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
215 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
216 r.v[base] = v[j];
217 base++;
218 }
219 }
220 r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR);
221 r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR);
214}
215
216void
217RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
218{
219 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
220
221 for (int i = 0; i < 31; ++i)

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233 for (int i = 0; i < NumVecV8ArchRegs; i++) {
234 auto v = (context->getWritableVecReg(
235 RegId(VecRegClass, i))).as<VecElem>();
236 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
237 v[j] = r.v[base];
238 base++;
239 }
240 }
222}
223
224void
225RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
226{
227 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
228
229 for (int i = 0; i < 31; ++i)

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241 for (int i = 0; i < NumVecV8ArchRegs; i++) {
242 auto v = (context->getWritableVecReg(
243 RegId(VecRegClass, i))).as<VecElem>();
244 for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
245 v[j] = r.v[base];
246 base++;
247 }
248 }
249 context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
250 context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
241}
242
243void
244RemoteGDB::AArch32GdbRegCache::getRegs(ThreadContext *context)
245{
246 DPRINTF(GDBAcc, "getRegs in remotegdb \n");
247
248 r.gpr[0] = context->readIntReg(INTREG_R0);

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256 r.gpr[8] = context->readIntReg(INTREG_R8);
257 r.gpr[9] = context->readIntReg(INTREG_R9);
258 r.gpr[10] = context->readIntReg(INTREG_R10);
259 r.gpr[11] = context->readIntReg(INTREG_R11);
260 r.gpr[12] = context->readIntReg(INTREG_R12);
261 r.gpr[13] = context->readIntReg(INTREG_SP);
262 r.gpr[14] = context->readIntReg(INTREG_LR);
263 r.gpr[15] = context->pcState().pc();
251}
252
253void
254RemoteGDB::AArch32GdbRegCache::getRegs(ThreadContext *context)
255{
256 DPRINTF(GDBAcc, "getRegs in remotegdb \n");
257
258 r.gpr[0] = context->readIntReg(INTREG_R0);

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266 r.gpr[8] = context->readIntReg(INTREG_R8);
267 r.gpr[9] = context->readIntReg(INTREG_R9);
268 r.gpr[10] = context->readIntReg(INTREG_R10);
269 r.gpr[11] = context->readIntReg(INTREG_R11);
270 r.gpr[12] = context->readIntReg(INTREG_R12);
271 r.gpr[13] = context->readIntReg(INTREG_SP);
272 r.gpr[14] = context->readIntReg(INTREG_LR);
273 r.gpr[15] = context->pcState().pc();
274 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
264
265 // One day somebody will implement transfer of FPRs correctly.
275
276 // One day somebody will implement transfer of FPRs correctly.
266 for (int i=0; i<8*3; i++) r.fpr[i] = 0;
277 for (int i = 0; i < 32; i++)
278 r.fpr[i] = 0;
267
268 r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR);
279
280 r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR);
269 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
270}
271
272void
273RemoteGDB::AArch32GdbRegCache::setRegs(ThreadContext *context) const
274{
275 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
276
277 context->setIntReg(INTREG_R0, r.gpr[0]);

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294 context->pcState(pc_state);
295
296 // One day somebody will implement transfer of FPRs correctly.
297
298 context->setMiscReg(MISCREG_FPSCR, r.fpscr);
299 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
300}
301
281}
282
283void
284RemoteGDB::AArch32GdbRegCache::setRegs(ThreadContext *context) const
285{
286 DPRINTF(GDBAcc, "setRegs in remotegdb \n");
287
288 context->setIntReg(INTREG_R0, r.gpr[0]);

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305 context->pcState(pc_state);
306
307 // One day somebody will implement transfer of FPRs correctly.
308
309 context->setMiscReg(MISCREG_FPSCR, r.fpscr);
310 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
311}
312
313bool
314RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
315{
316#define GDB_XML(x, s) \
317 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
318 Blobs::s ## _len) }
319 static const std::map<std::string, std::string> annexMap32{
320 GDB_XML("target.xml", gdb_xml_arm_target),
321 GDB_XML("arm-core.xml", gdb_xml_arm_core),
322 GDB_XML("arm-vfpv3.xml", gdb_xml_arm_vfpv3),
323 };
324 static const std::map<std::string, std::string> annexMap64{
325 GDB_XML("target.xml", gdb_xml_aarch64_target),
326 GDB_XML("aarch64-core.xml", gdb_xml_aarch64_core),
327 GDB_XML("aarch64-fpu.xml", gdb_xml_aarch64_fpu),
328 };
329#undef GDB_XML
330 auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32;
331 auto it = annexMap.find(annex);
332 if (it == annexMap.end())
333 return false;
334 output = it->second;
335 return true;
336}
337
302BaseGdbRegCache*
303RemoteGDB::gdbRegs()
304{
305 if (inAArch64(context()))
306 return &regCache64;
307 else
308 return &regCache32;
309}
338BaseGdbRegCache*
339RemoteGDB::gdbRegs()
340{
341 if (inAArch64(context()))
342 return &regCache64;
343 else
344 return &regCache32;
345}