remote_gdb.cc (10708:fe09d1bc6721) | remote_gdb.cc (11274:d9a0136ab8cc) |
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1/* | 1/* |
2 * Copyright 2015 LabWare |
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2 * Copyright 2014 Google Inc. 3 * Copyright (c) 2010, 2013 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software --- 25 unchanged lines hidden (view full) --- 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Nathan Binkert 42 * William Wang | 3 * Copyright 2014 Google Inc. 4 * Copyright (c) 2010, 2013 ARM Limited 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software --- 25 unchanged lines hidden (view full) --- 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Nathan Binkert 43 * William Wang |
44 * Boris Shingarov |
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43 */ 44 45/* 46 * Copyright (c) 1990, 1993 The Regents of the University of California 47 * All rights reserved 48 * 49 * This software was developed by the Computer Systems Engineering group 50 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and --- 106 unchanged lines hidden (view full) --- 157#include "mem/port.hh" 158#include "sim/full_system.hh" 159#include "sim/system.hh" 160 161using namespace std; 162using namespace ArmISA; 163 164RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) | 45 */ 46 47/* 48 * Copyright (c) 1990, 1993 The Regents of the University of California 49 * All rights reserved 50 * 51 * This software was developed by the Computer Systems Engineering group 52 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and --- 106 unchanged lines hidden (view full) --- 159#include "mem/port.hh" 160#include "sim/full_system.hh" 161#include "sim/system.hh" 162 163using namespace std; 164using namespace ArmISA; 165 166RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) |
165 : BaseRemoteGDB(_system, tc, GDB_REG_BYTES) | 167 : BaseRemoteGDB(_system, tc) |
166{ 167} 168 169/* 170 * Determine if the mapping at va..(va+len) is valid. 171 */ 172bool 173RemoteGDB::acc(Addr va, size_t len) --- 13 unchanged lines hidden (view full) --- 187 //Check to make sure the first byte is mapped into the processes address 188 //space. 189 if (context->getProcessPtr()->pTable->lookup(va, entry)) 190 return true; 191 return false; 192 } 193} 194 | 168{ 169} 170 171/* 172 * Determine if the mapping at va..(va+len) is valid. 173 */ 174bool 175RemoteGDB::acc(Addr va, size_t len) --- 13 unchanged lines hidden (view full) --- 189 //Check to make sure the first byte is mapped into the processes address 190 //space. 191 if (context->getProcessPtr()->pTable->lookup(va, entry)) 192 return true; 193 return false; 194 } 195} 196 |
195/* 196 * Translate the kernel debugger register format into the GDB register 197 * format. 198 */ | |
199void | 197void |
200RemoteGDB::getregs() | 198RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context) |
201{ | 199{ |
202 DPRINTF(GDBAcc, "getregs in remotegdb \n"); | 200 DPRINTF(GDBAcc, "getRegs in remotegdb \n"); |
203 | 201 |
204 memset(gdbregs.regs, 0, gdbregs.bytes()); | 202 for (int i = 0; i < 31; ++i) 203 r.x[i] = context->readIntReg(INTREG_X0 + i); 204 r.spx = context->readIntReg(INTREG_SPX); 205 r.pc = context->pcState().pc(); 206 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR); |
205 | 207 |
206 if (inAArch64(context)) { // AArch64 207 // x0-x30 208 for (int i = 0; i < 31; ++i) 209 gdbregs.regs64[GDB64_X0 + i] = context->readIntReg(INTREG_X0 + i); 210 gdbregs.regs64[GDB64_SPX] = context->readIntReg(INTREG_SPX); 211 // pc 212 gdbregs.regs64[GDB64_PC] = context->pcState().pc(); 213 // cpsr 214 gdbregs.regs64[GDB64_CPSR] = 215 context->readMiscRegNoEffect(MISCREG_CPSR); 216 // v0-v31 217 for (int i = 0; i < 128; i += 4) { 218 int gdboff = GDB64_V0_32 + i; 219 gdbregs.regs32[gdboff + 0] = context->readFloatRegBits(i + 2); 220 gdbregs.regs32[gdboff + 1] = context->readFloatRegBits(i + 3); 221 gdbregs.regs32[gdboff + 2] = context->readFloatRegBits(i + 0); 222 gdbregs.regs32[gdboff + 3] = context->readFloatRegBits(i + 1); 223 } 224 } else { // AArch32 225 // R0-R15 supervisor mode 226 gdbregs.regs32[GDB32_R0 + 0] = context->readIntReg(INTREG_R0); 227 gdbregs.regs32[GDB32_R0 + 1] = context->readIntReg(INTREG_R1); 228 gdbregs.regs32[GDB32_R0 + 2] = context->readIntReg(INTREG_R2); 229 gdbregs.regs32[GDB32_R0 + 3] = context->readIntReg(INTREG_R3); 230 gdbregs.regs32[GDB32_R0 + 4] = context->readIntReg(INTREG_R4); 231 gdbregs.regs32[GDB32_R0 + 5] = context->readIntReg(INTREG_R5); 232 gdbregs.regs32[GDB32_R0 + 6] = context->readIntReg(INTREG_R6); 233 gdbregs.regs32[GDB32_R0 + 7] = context->readIntReg(INTREG_R7); 234 gdbregs.regs32[GDB32_R0 + 8] = context->readIntReg(INTREG_R8); 235 gdbregs.regs32[GDB32_R0 + 9] = context->readIntReg(INTREG_R9); 236 gdbregs.regs32[GDB32_R0 + 10] = context->readIntReg(INTREG_R10); 237 gdbregs.regs32[GDB32_R0 + 11] = context->readIntReg(INTREG_R11); 238 gdbregs.regs32[GDB32_R0 + 12] = context->readIntReg(INTREG_R12); 239 gdbregs.regs32[GDB32_R0 + 13] = context->readIntReg(INTREG_SP); 240 gdbregs.regs32[GDB32_R0 + 14] = context->readIntReg(INTREG_LR); 241 gdbregs.regs32[GDB32_R0 + 15] = context->pcState().pc(); | 208 for (int i = 0; i < 32*4; i += 4) { 209 r.v[i + 0] = context->readFloatRegBits(i + 2); 210 r.v[i + 1] = context->readFloatRegBits(i + 3); 211 r.v[i + 2] = context->readFloatRegBits(i + 0); 212 r.v[i + 3] = context->readFloatRegBits(i + 1); 213 } 214} |
242 | 215 |
243 // CPSR 244 gdbregs.regs32[GDB32_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR); | 216void 217RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const 218{ 219 DPRINTF(GDBAcc, "setRegs in remotegdb \n"); |
245 | 220 |
246 // vfpv3/neon floating point registers (32 double or 64 float) 247 for (int i = 0; i < NumFloatV7ArchRegs; ++i) 248 gdbregs.regs32[GDB32_F0 + i] = context->readFloatRegBits(i); | 221 for (int i = 0; i < 31; ++i) 222 context->setIntReg(INTREG_X0 + i, r.x[i]); 223 context->pcState(r.pc); 224 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr); 225 // Update the stack pointer. This should be done after 226 // updating CPSR/PSTATE since that might affect how SPX gets 227 // mapped. 228 context->setIntReg(INTREG_SPX, r.spx); |
249 | 229 |
250 // FPSCR 251 gdbregs.regs32[GDB32_FPSCR] = 252 context->readMiscRegNoEffect(MISCREG_FPSCR); | 230 for (int i = 0; i < 32*4; i += 4) { 231 context->setFloatRegBits(i + 2, r.v[i + 0]); 232 context->setFloatRegBits(i + 3, r.v[i + 1]); 233 context->setFloatRegBits(i + 0, r.v[i + 2]); 234 context->setFloatRegBits(i + 1, r.v[i + 3]); |
253 } 254} 255 | 235 } 236} 237 |
256/* 257 * Translate the GDB register format into the kernel debugger register 258 * format. 259 */ | |
260void | 238void |
261RemoteGDB::setregs() | 239RemoteGDB::AArch32GdbRegCache::getRegs(ThreadContext *context) |
262{ | 240{ |
241 DPRINTF(GDBAcc, "getRegs in remotegdb \n"); |
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263 | 242 |
264 DPRINTF(GDBAcc, "setregs in remotegdb \n"); 265 if (inAArch64(context)) { // AArch64 266 // x0-x30 267 for (int i = 0; i < 31; ++i) 268 context->setIntReg(INTREG_X0 + i, gdbregs.regs64[GDB64_X0 + i]); 269 // pc 270 context->pcState(gdbregs.regs64[GDB64_PC]); 271 // cpsr 272 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs64[GDB64_CPSR]); 273 // Update the stack pointer. This should be done after 274 // updating CPSR/PSTATE since that might affect how SPX gets 275 // mapped. 276 context->setIntReg(INTREG_SPX, gdbregs.regs64[GDB64_SPX]); 277 // v0-v31 278 for (int i = 0; i < 128; i += 4) { 279 int gdboff = GDB64_V0_32 + i; 280 context->setFloatRegBits(i + 2, gdbregs.regs32[gdboff + 0]); 281 context->setFloatRegBits(i + 3, gdbregs.regs32[gdboff + 1]); 282 context->setFloatRegBits(i + 0, gdbregs.regs32[gdboff + 2]); 283 context->setFloatRegBits(i + 1, gdbregs.regs32[gdboff + 3]); 284 } 285 } else { // AArch32 286 // R0-R15 supervisor mode 287 // arm registers are 32 bits wide, gdb registers are 64 bits wide 288 // two arm registers are packed into one gdb register (little endian) 289 context->setIntReg(INTREG_R0, gdbregs.regs32[GDB32_R0 + 0]); 290 context->setIntReg(INTREG_R1, gdbregs.regs32[GDB32_R0 + 1]); 291 context->setIntReg(INTREG_R2, gdbregs.regs32[GDB32_R0 + 2]); 292 context->setIntReg(INTREG_R3, gdbregs.regs32[GDB32_R0 + 3]); 293 context->setIntReg(INTREG_R4, gdbregs.regs32[GDB32_R0 + 4]); 294 context->setIntReg(INTREG_R5, gdbregs.regs32[GDB32_R0 + 5]); 295 context->setIntReg(INTREG_R6, gdbregs.regs32[GDB32_R0 + 6]); 296 context->setIntReg(INTREG_R7, gdbregs.regs32[GDB32_R0 + 7]); 297 context->setIntReg(INTREG_R8, gdbregs.regs32[GDB32_R0 + 8]); 298 context->setIntReg(INTREG_R9, gdbregs.regs32[GDB32_R0 + 9]); 299 context->setIntReg(INTREG_R10, gdbregs.regs32[GDB32_R0 + 10]); 300 context->setIntReg(INTREG_R11, gdbregs.regs32[GDB32_R0 + 11]); 301 context->setIntReg(INTREG_R12, gdbregs.regs32[GDB32_R0 + 12]); 302 context->setIntReg(INTREG_SP, gdbregs.regs32[GDB32_R0 + 13]); 303 context->setIntReg(INTREG_LR, gdbregs.regs32[GDB32_R0 + 14]); 304 context->pcState(gdbregs.regs32[GDB32_R0 + 7]); | 243 r.gpr[0] = context->readIntReg(INTREG_R0); 244 r.gpr[1] = context->readIntReg(INTREG_R1); 245 r.gpr[2] = context->readIntReg(INTREG_R2); 246 r.gpr[3] = context->readIntReg(INTREG_R3); 247 r.gpr[4] = context->readIntReg(INTREG_R4); 248 r.gpr[5] = context->readIntReg(INTREG_R5); 249 r.gpr[6] = context->readIntReg(INTREG_R6); 250 r.gpr[7] = context->readIntReg(INTREG_R7); 251 r.gpr[8] = context->readIntReg(INTREG_R8); 252 r.gpr[9] = context->readIntReg(INTREG_R9); 253 r.gpr[10] = context->readIntReg(INTREG_R10); 254 r.gpr[11] = context->readIntReg(INTREG_R11); 255 r.gpr[12] = context->readIntReg(INTREG_R12); 256 r.gpr[13] = context->readIntReg(INTREG_SP); 257 r.gpr[14] = context->readIntReg(INTREG_LR); 258 r.gpr[15] = context->pcState().pc(); |
305 | 259 |
306 //CPSR 307 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs32[GDB32_CPSR]); | 260 // One day somebody will implement transfer of FPRs correctly. 261 for (int i=0; i<8*3; i++) r.fpr[i] = 0; |
308 | 262 |
309 //vfpv3/neon floating point registers (32 double or 64 float) 310 for (int i = 0; i < NumFloatV7ArchRegs; ++i) 311 context->setFloatRegBits(i, gdbregs.regs32[GDB32_F0 + i]); 312 313 //FPSCR 314 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs32[GDB32_FPSCR]); 315 } | 263 r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR); 264 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR); |
316} 317 | 265} 266 |
318// Write bytes to kernel address space for debugger. 319bool 320RemoteGDB::write(Addr vaddr, size_t size, const char *data) | 267void 268RemoteGDB::AArch32GdbRegCache::setRegs(ThreadContext *context) const |
321{ | 269{ |
322 return BaseRemoteGDB::write(vaddr, size, data); | 270 DPRINTF(GDBAcc, "setRegs in remotegdb \n"); 271 272 context->setIntReg(INTREG_R0, r.gpr[0]); 273 context->setIntReg(INTREG_R1, r.gpr[1]); 274 context->setIntReg(INTREG_R2, r.gpr[2]); 275 context->setIntReg(INTREG_R3, r.gpr[3]); 276 context->setIntReg(INTREG_R4, r.gpr[4]); 277 context->setIntReg(INTREG_R5, r.gpr[5]); 278 context->setIntReg(INTREG_R6, r.gpr[6]); 279 context->setIntReg(INTREG_R7, r.gpr[7]); 280 context->setIntReg(INTREG_R8, r.gpr[8]); 281 context->setIntReg(INTREG_R9, r.gpr[9]); 282 context->setIntReg(INTREG_R10, r.gpr[10]); 283 context->setIntReg(INTREG_R11, r.gpr[11]); 284 context->setIntReg(INTREG_R12, r.gpr[12]); 285 context->setIntReg(INTREG_SP, r.gpr[13]); 286 context->setIntReg(INTREG_LR, r.gpr[14]); 287 context->pcState(r.gpr[15]); 288 289 // One day somebody will implement transfer of FPRs correctly. 290 291 context->setMiscReg(MISCREG_FPSCR, r.fpscr); 292 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr); |
323} 324 | 293} 294 |
295RemoteGDB::BaseGdbRegCache* 296RemoteGDB::gdbRegs() 297{ 298 if (inAArch64(context)) 299 return new AArch64GdbRegCache(this); 300 else 301 return new AArch32GdbRegCache(this); 302} |
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