1/* |
2 * Copyright (c) 2010, 2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 122 unchanged lines hidden (view full) --- 133#include <unistd.h> 134 135#include <string> 136 137#include "arch/arm/decoder.hh" 138#include "arch/arm/pagetable.hh" 139#include "arch/arm/registers.hh" 140#include "arch/arm/remote_gdb.hh" |
141#include "arch/arm/system.hh" |
142#include "arch/arm/utility.hh" 143#include "arch/arm/vtophys.hh" 144#include "base/intmath.hh" 145#include "base/remote_gdb.hh" 146#include "base/socket.hh" 147#include "base/trace.hh" 148#include "cpu/static_inst.hh" 149#include "cpu/thread_context.hh" --- 5 unchanged lines hidden (view full) --- 155#include "mem/port.hh" 156#include "sim/full_system.hh" 157#include "sim/system.hh" 158 159using namespace std; 160using namespace ArmISA; 161 162RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) |
163 : BaseRemoteGDB(_system, tc, MAX_NUMREGS) |
164{ 165} 166 167/* 168 * Determine if the mapping at va..(va+len) is valid. 169 */ 170bool 171RemoteGDB::acc(Addr va, size_t len) --- 28 unchanged lines hidden (view full) --- 200 */ 201void 202RemoteGDB::getregs() 203{ 204 DPRINTF(GDBAcc, "getregs in remotegdb \n"); 205 206 memset(gdbregs.regs, 0, gdbregs.bytes()); 207 |
208 if (inAArch64(context)) { // AArch64 209 // x0-x31 210 for (int i = 0; i < 32; ++i) { 211 gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i); 212 } 213 // pc 214 gdbregs.regs[REG_PC_64] = context->pcState().pc(); 215 // cpsr 216 gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR); 217 // v0-v31 218 for (int i = 0; i < 32; ++i) { 219 gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>( 220 context->readFloatRegBits(i * 4 + 3)) << 32 | 221 context->readFloatRegBits(i * 4 + 2); 222 gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>( 223 context->readFloatRegBits(i * 4 + 1)) << 32 | 224 context->readFloatRegBits(i * 4 + 0); 225 } 226 } else { // AArch32 227 // R0-R15 supervisor mode 228 // arm registers are 32 bits wide, gdb registers are 64 bits wide two 229 // arm registers are packed into one gdb register (little endian) 230 gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 | 231 context->readIntReg(INTREG_R0); 232 gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 | 233 context->readIntReg(INTREG_R2); 234 gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 | 235 context->readIntReg(INTREG_R4); 236 gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 | 237 context->readIntReg(INTREG_R6); 238 gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 | 239 context->readIntReg(INTREG_R8); 240 gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32| 241 context->readIntReg(INTREG_R10); 242 gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 | 243 context->readIntReg(INTREG_R12); 244 gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 | 245 context->readIntReg(INTREG_LR); |
246 |
247 // CPSR 248 gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR); |
249 |
250 // vfpv3/neon floating point registers (32 double or 64 float) |
251 |
252 gdbregs.regs[REG_F0] = 253 static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 | 254 gdbregs.regs[REG_CPSR]; |
255 |
256 for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) { 257 gdbregs.regs[i + REG_F0] = 258 static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 | 259 context->readFloatRegBits(2*i-1); 260 } |
261 |
262 // FPSCR 263 gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>( 264 context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 | 265 context->readFloatRegBits(NumFloatV7ArchRegs - 1); 266 } |
267} 268 269/* 270 * Translate the GDB register format into the kernel debugger register 271 * format. 272 */ 273void 274RemoteGDB::setregs() 275{ 276 277 DPRINTF(GDBAcc, "setregs in remotegdb \n"); |
278 if (inAArch64(context)) { // AArch64 279 // x0-x31 280 for (int i = 0; i < 32; ++i) { 281 context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]); 282 } 283 // pc 284 context->pcState(gdbregs.regs[REG_PC_64]); 285 // cpsr 286 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]); 287 // v0-v31 288 for (int i = 0; i < 32; ++i) { 289 context->setFloatRegBits(i * 4 + 3, 290 gdbregs.regs[REG_V0 + 2 * i] >> 32); 291 context->setFloatRegBits(i * 4 + 2, 292 gdbregs.regs[REG_V0 + 2 * i]); 293 context->setFloatRegBits(i * 4 + 1, 294 gdbregs.regs[REG_V0 + 2 * i + 1] >> 32); 295 context->setFloatRegBits(i * 4 + 0, 296 gdbregs.regs[REG_V0 + 2 * i + 1]); 297 } 298 } else { // AArch32 299 // R0-R15 supervisor mode 300 // arm registers are 32 bits wide, gdb registers are 64 bits wide 301 // two arm registers are packed into one gdb register (little endian) 302 context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0)); 303 context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32)); 304 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0)); 305 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32)); 306 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0)); 307 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32)); 308 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0)); 309 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32)); 310 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0)); 311 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32)); 312 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0)); 313 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32)); 314 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0)); 315 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32)); 316 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0)); 317 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32)); |
318 |
319 //CPSR 320 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]); |
321 |
322 //vfpv3/neon floating point registers (32 double or 64 float) 323 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32); |
324 |
325 for (int i = 1; i < NumFloatV7ArchRegs; ++i) { 326 if (i%2) { 327 int j = (i+1)/2; 328 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0)); 329 } else { 330 int j = i/2; 331 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32); 332 } 333 } |
334 |
335 //FPSCR 336 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32); |
337 } |
338} 339 340void 341RemoteGDB::clearSingleStep() 342{ 343 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", 344 takenBkpt, notTakenBkpt); 345 --- 41 unchanged lines hidden --- |