1/* 2 * Copyright 2015 LabWare 3 * Copyright 2014 Google Inc. |
4 * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited |
5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software 11 * licensed hereunder. You may use the software subject to the license 12 * terms below provided that you ensure that this notice is replicated --- 132 unchanged lines hidden (view full) --- 145#include "arch/arm/system.hh" 146#include "arch/arm/utility.hh" 147#include "arch/arm/vtophys.hh" 148#include "base/chunk_generator.hh" 149#include "base/intmath.hh" 150#include "base/remote_gdb.hh" 151#include "base/socket.hh" 152#include "base/trace.hh" |
153#include "blobs/gdb_xml_aarch64_core.hh" 154#include "blobs/gdb_xml_aarch64_fpu.hh" 155#include "blobs/gdb_xml_aarch64_target.hh" 156#include "blobs/gdb_xml_arm_core.hh" 157#include "blobs/gdb_xml_arm_target.hh" 158#include "blobs/gdb_xml_arm_vfpv3.hh" |
159#include "cpu/static_inst.hh" 160#include "cpu/thread_context.hh" 161#include "cpu/thread_state.hh" 162#include "debug/GDBAcc.hh" 163#include "debug/GDBMisc.hh" 164#include "mem/page_table.hh" 165#include "mem/physical.hh" 166#include "mem/port.hh" --- 45 unchanged lines hidden (view full) --- 212 size_t base = 0; 213 for (int i = 0; i < NumVecV8ArchRegs; i++) { 214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>(); 215 for (size_t j = 0; j < NumVecElemPerVecReg; j++) { 216 r.v[base] = v[j]; 217 base++; 218 } 219 } |
220 r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR); 221 r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR); |
222} 223 224void 225RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const 226{ 227 DPRINTF(GDBAcc, "setRegs in remotegdb \n"); 228 229 for (int i = 0; i < 31; ++i) --- 11 unchanged lines hidden (view full) --- 241 for (int i = 0; i < NumVecV8ArchRegs; i++) { 242 auto v = (context->getWritableVecReg( 243 RegId(VecRegClass, i))).as<VecElem>(); 244 for (size_t j = 0; j < NumVecElemPerVecReg; j++) { 245 v[j] = r.v[base]; 246 base++; 247 } 248 } |
249 context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr); 250 context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr); |
251} 252 253void 254RemoteGDB::AArch32GdbRegCache::getRegs(ThreadContext *context) 255{ 256 DPRINTF(GDBAcc, "getRegs in remotegdb \n"); 257 258 r.gpr[0] = context->readIntReg(INTREG_R0); --- 7 unchanged lines hidden (view full) --- 266 r.gpr[8] = context->readIntReg(INTREG_R8); 267 r.gpr[9] = context->readIntReg(INTREG_R9); 268 r.gpr[10] = context->readIntReg(INTREG_R10); 269 r.gpr[11] = context->readIntReg(INTREG_R11); 270 r.gpr[12] = context->readIntReg(INTREG_R12); 271 r.gpr[13] = context->readIntReg(INTREG_SP); 272 r.gpr[14] = context->readIntReg(INTREG_LR); 273 r.gpr[15] = context->pcState().pc(); |
274 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR); |
275 276 // One day somebody will implement transfer of FPRs correctly. |
277 for (int i = 0; i < 32; i++) 278 r.fpr[i] = 0; |
279 280 r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR); |
281} 282 283void 284RemoteGDB::AArch32GdbRegCache::setRegs(ThreadContext *context) const 285{ 286 DPRINTF(GDBAcc, "setRegs in remotegdb \n"); 287 288 context->setIntReg(INTREG_R0, r.gpr[0]); --- 16 unchanged lines hidden (view full) --- 305 context->pcState(pc_state); 306 307 // One day somebody will implement transfer of FPRs correctly. 308 309 context->setMiscReg(MISCREG_FPSCR, r.fpscr); 310 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr); 311} 312 |
313bool 314RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output) 315{ 316#define GDB_XML(x, s) \ 317 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \ 318 Blobs::s ## _len) } 319 static const std::map<std::string, std::string> annexMap32{ 320 GDB_XML("target.xml", gdb_xml_arm_target), 321 GDB_XML("arm-core.xml", gdb_xml_arm_core), 322 GDB_XML("arm-vfpv3.xml", gdb_xml_arm_vfpv3), 323 }; 324 static const std::map<std::string, std::string> annexMap64{ 325 GDB_XML("target.xml", gdb_xml_aarch64_target), 326 GDB_XML("aarch64-core.xml", gdb_xml_aarch64_core), 327 GDB_XML("aarch64-fpu.xml", gdb_xml_aarch64_fpu), 328 }; 329#undef GDB_XML 330 auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32; 331 auto it = annexMap.find(annex); 332 if (it == annexMap.end()) 333 return false; 334 output = it->second; 335 return true; 336} 337 |
338BaseGdbRegCache* 339RemoteGDB::gdbRegs() 340{ 341 if (inAArch64(context())) 342 return ®Cache64; 343 else 344 return ®Cache32; 345} |