1/*
2 * Copyright (c) 2010, 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 * William Wang
42 */
43
44/*
45 * Copyright (c) 1990, 1993 The Regents of the University of California
46 * All rights reserved
47 *
48 * This software was developed by the Computer Systems Engineering group
49 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
50 * contributed to Berkeley.
51 *
52 * All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by the University of
55 * California, Lawrence Berkeley Laboratories.
56 *
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
59 * are met:
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
65 * 3. All advertising materials mentioning features or use of this software
66 * must display the following acknowledgement:
67 * This product includes software developed by the University of
68 * California, Berkeley and its contributors.
69 * 4. Neither the name of the University nor the names of its contributors
70 * may be used to endorse or promote products derived from this software
71 * without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
83 * SUCH DAMAGE.
84 *
85 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
86 */
87
88/*-
89 * Copyright (c) 2001 The NetBSD Foundation, Inc.
90 * All rights reserved.
91 *
92 * This code is derived from software contributed to The NetBSD Foundation
93 * by Jason R. Thorpe.
94 *
95 * Redistribution and use in source and binary forms, with or without
96 * modification, are permitted provided that the following conditions
97 * are met:
98 * 1. Redistributions of source code must retain the above copyright
99 * notice, this list of conditions and the following disclaimer.
100 * 2. Redistributions in binary form must reproduce the above copyright
101 * notice, this list of conditions and the following disclaimer in the
102 * documentation and/or other materials provided with the distribution.
103 * 3. All advertising materials mentioning features or use of this software
104 * must display the following acknowledgement:
105 * This product includes software developed by the NetBSD
106 * Foundation, Inc. and its contributors.
107 * 4. Neither the name of The NetBSD Foundation nor the names of its
108 * contributors may be used to endorse or promote products derived
109 * from this software without specific prior written permission.
110 *
111 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
112 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
113 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
114 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
115 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
116 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
117 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
118 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
119 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
120 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
121 * POSSIBILITY OF SUCH DAMAGE.
122 */
123
124/*
125 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
126 *
127 * Taken from NetBSD
128 *
129 * "Stub" to allow remote cpu to debug over a serial line using gdb.
130 */
131
132#include <sys/signal.h>
133#include <unistd.h>
134
135#include <string>
136
137#include "arch/arm/decoder.hh"
138#include "arch/arm/pagetable.hh"
139#include "arch/arm/registers.hh"
140#include "arch/arm/remote_gdb.hh"
141#include "arch/arm/system.hh"
142#include "arch/arm/utility.hh"
143#include "arch/arm/vtophys.hh"
144#include "base/intmath.hh"
145#include "base/remote_gdb.hh"
146#include "base/socket.hh"
147#include "base/trace.hh"
148#include "cpu/static_inst.hh"
149#include "cpu/thread_context.hh"
150#include "cpu/thread_state.hh"
151#include "debug/GDBAcc.hh"
152#include "debug/GDBMisc.hh"
153#include "mem/page_table.hh"
154#include "mem/physical.hh"
155#include "mem/port.hh"
156#include "sim/full_system.hh"
157#include "sim/system.hh"
158
159using namespace std;
160using namespace ArmISA;
161
162RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
| 1/*
2 * Copyright (c) 2010, 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 * William Wang
42 */
43
44/*
45 * Copyright (c) 1990, 1993 The Regents of the University of California
46 * All rights reserved
47 *
48 * This software was developed by the Computer Systems Engineering group
49 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
50 * contributed to Berkeley.
51 *
52 * All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by the University of
55 * California, Lawrence Berkeley Laboratories.
56 *
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
59 * are met:
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
65 * 3. All advertising materials mentioning features or use of this software
66 * must display the following acknowledgement:
67 * This product includes software developed by the University of
68 * California, Berkeley and its contributors.
69 * 4. Neither the name of the University nor the names of its contributors
70 * may be used to endorse or promote products derived from this software
71 * without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
83 * SUCH DAMAGE.
84 *
85 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
86 */
87
88/*-
89 * Copyright (c) 2001 The NetBSD Foundation, Inc.
90 * All rights reserved.
91 *
92 * This code is derived from software contributed to The NetBSD Foundation
93 * by Jason R. Thorpe.
94 *
95 * Redistribution and use in source and binary forms, with or without
96 * modification, are permitted provided that the following conditions
97 * are met:
98 * 1. Redistributions of source code must retain the above copyright
99 * notice, this list of conditions and the following disclaimer.
100 * 2. Redistributions in binary form must reproduce the above copyright
101 * notice, this list of conditions and the following disclaimer in the
102 * documentation and/or other materials provided with the distribution.
103 * 3. All advertising materials mentioning features or use of this software
104 * must display the following acknowledgement:
105 * This product includes software developed by the NetBSD
106 * Foundation, Inc. and its contributors.
107 * 4. Neither the name of The NetBSD Foundation nor the names of its
108 * contributors may be used to endorse or promote products derived
109 * from this software without specific prior written permission.
110 *
111 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
112 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
113 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
114 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
115 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
116 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
117 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
118 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
119 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
120 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
121 * POSSIBILITY OF SUCH DAMAGE.
122 */
123
124/*
125 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
126 *
127 * Taken from NetBSD
128 *
129 * "Stub" to allow remote cpu to debug over a serial line using gdb.
130 */
131
132#include <sys/signal.h>
133#include <unistd.h>
134
135#include <string>
136
137#include "arch/arm/decoder.hh"
138#include "arch/arm/pagetable.hh"
139#include "arch/arm/registers.hh"
140#include "arch/arm/remote_gdb.hh"
141#include "arch/arm/system.hh"
142#include "arch/arm/utility.hh"
143#include "arch/arm/vtophys.hh"
144#include "base/intmath.hh"
145#include "base/remote_gdb.hh"
146#include "base/socket.hh"
147#include "base/trace.hh"
148#include "cpu/static_inst.hh"
149#include "cpu/thread_context.hh"
150#include "cpu/thread_state.hh"
151#include "debug/GDBAcc.hh"
152#include "debug/GDBMisc.hh"
153#include "mem/page_table.hh"
154#include "mem/physical.hh"
155#include "mem/port.hh"
156#include "sim/full_system.hh"
157#include "sim/system.hh"
158
159using namespace std;
160using namespace ArmISA;
161
162RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
|
164{
165}
166
167/*
168 * Determine if the mapping at va..(va+len) is valid.
169 */
170bool
171RemoteGDB::acc(Addr va, size_t len)
172{
173 if (FullSystem) {
174 Addr last_va;
175 va = truncPage(va);
176 last_va = roundPage(va + len);
177
178 do {
179 if (virtvalid(context, va)) {
180 return true;
181 }
182 va += PageBytes;
183 } while (va < last_va);
184
185 DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
186 return true;
187 } else {
188 TlbEntry entry;
189 //Check to make sure the first byte is mapped into the processes address
190 //space.
191 if (context->getProcessPtr()->pTable->lookup(va, entry))
192 return true;
193 return false;
194 }
195}
196
197/*
198 * Translate the kernel debugger register format into the GDB register
199 * format.
200 */
201void
202RemoteGDB::getregs()
203{
204 DPRINTF(GDBAcc, "getregs in remotegdb \n");
205
206 memset(gdbregs.regs, 0, gdbregs.bytes());
207
208 if (inAArch64(context)) { // AArch64
209 // x0-x31
210 for (int i = 0; i < 32; ++i) {
211 gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i);
212 }
213 // pc
214 gdbregs.regs[REG_PC_64] = context->pcState().pc();
215 // cpsr
216 gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR);
217 // v0-v31
218 for (int i = 0; i < 32; ++i) {
219 gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>(
220 context->readFloatRegBits(i * 4 + 3)) << 32 |
221 context->readFloatRegBits(i * 4 + 2);
222 gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>(
223 context->readFloatRegBits(i * 4 + 1)) << 32 |
224 context->readFloatRegBits(i * 4 + 0);
225 }
226 } else { // AArch32
227 // R0-R15 supervisor mode
228 // arm registers are 32 bits wide, gdb registers are 64 bits wide two
229 // arm registers are packed into one gdb register (little endian)
230 gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 |
231 context->readIntReg(INTREG_R0);
232 gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 |
233 context->readIntReg(INTREG_R2);
234 gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 |
235 context->readIntReg(INTREG_R4);
236 gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 |
237 context->readIntReg(INTREG_R6);
238 gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 |
239 context->readIntReg(INTREG_R8);
240 gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32|
241 context->readIntReg(INTREG_R10);
242 gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 |
243 context->readIntReg(INTREG_R12);
244 gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 |
245 context->readIntReg(INTREG_LR);
246
247 // CPSR
248 gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
249
250 // vfpv3/neon floating point registers (32 double or 64 float)
251
252 gdbregs.regs[REG_F0] =
253 static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 |
254 gdbregs.regs[REG_CPSR];
255
256 for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) {
257 gdbregs.regs[i + REG_F0] =
258 static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 |
259 context->readFloatRegBits(2*i-1);
260 }
261
262 // FPSCR
263 gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>(
264 context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 |
265 context->readFloatRegBits(NumFloatV7ArchRegs - 1);
266 }
267}
268
269/*
270 * Translate the GDB register format into the kernel debugger register
271 * format.
272 */
273void
274RemoteGDB::setregs()
275{
276
277 DPRINTF(GDBAcc, "setregs in remotegdb \n");
278 if (inAArch64(context)) { // AArch64
279 // x0-x31
280 for (int i = 0; i < 32; ++i) {
281 context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]);
282 }
283 // pc
284 context->pcState(gdbregs.regs[REG_PC_64]);
285 // cpsr
286 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]);
287 // v0-v31
288 for (int i = 0; i < 32; ++i) {
289 context->setFloatRegBits(i * 4 + 3,
290 gdbregs.regs[REG_V0 + 2 * i] >> 32);
291 context->setFloatRegBits(i * 4 + 2,
292 gdbregs.regs[REG_V0 + 2 * i]);
293 context->setFloatRegBits(i * 4 + 1,
294 gdbregs.regs[REG_V0 + 2 * i + 1] >> 32);
295 context->setFloatRegBits(i * 4 + 0,
296 gdbregs.regs[REG_V0 + 2 * i + 1]);
297 }
298 } else { // AArch32
299 // R0-R15 supervisor mode
300 // arm registers are 32 bits wide, gdb registers are 64 bits wide
301 // two arm registers are packed into one gdb register (little endian)
302 context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0));
303 context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32));
304 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0));
305 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32));
306 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0));
307 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32));
308 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0));
309 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32));
310 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0));
311 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32));
312 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0));
313 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32));
314 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0));
315 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32));
316 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0));
317 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32));
318
319 //CPSR
320 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]);
321
322 //vfpv3/neon floating point registers (32 double or 64 float)
323 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32);
324
325 for (int i = 1; i < NumFloatV7ArchRegs; ++i) {
326 if (i%2) {
327 int j = (i+1)/2;
328 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0));
329 } else {
330 int j = i/2;
331 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32);
332 }
333 }
334
335 //FPSCR
336 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
337 }
338}
339
340void
341RemoteGDB::clearSingleStep()
342{
343 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
344 takenBkpt, notTakenBkpt);
345
346 if (takenBkpt != 0)
347 clearTempBreakpoint(takenBkpt);
348
349 if (notTakenBkpt != 0)
350 clearTempBreakpoint(notTakenBkpt);
351}
352
353void
354RemoteGDB::setSingleStep()
355{
356 PCState pc = context->pcState();
357 PCState bpc;
358 bool set_bt = false;
359
360 // User was stopped at pc, e.g. the instruction at pc was not
361 // executed.
362 MachInst inst = read<MachInst>(pc.pc());
363 StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc());
364 if (si->hasBranchTarget(pc, context, bpc)) {
365 // Don't bother setting a breakpoint on the taken branch if it
366 // is the same as the next pc
367 if (bpc.pc() != pc.npc())
368 set_bt = true;
369 }
370
371 DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n",
372 takenBkpt, notTakenBkpt);
373
374 setTempBreakpoint(notTakenBkpt = pc.npc());
375
376 if (set_bt)
377 setTempBreakpoint(takenBkpt = bpc.pc());
378}
379
380// Write bytes to kernel address space for debugger.
381bool
382RemoteGDB::write(Addr vaddr, size_t size, const char *data)
383{
384 return BaseRemoteGDB::write(vaddr, size, data);
385}
386
| 164{
165}
166
167/*
168 * Determine if the mapping at va..(va+len) is valid.
169 */
170bool
171RemoteGDB::acc(Addr va, size_t len)
172{
173 if (FullSystem) {
174 Addr last_va;
175 va = truncPage(va);
176 last_va = roundPage(va + len);
177
178 do {
179 if (virtvalid(context, va)) {
180 return true;
181 }
182 va += PageBytes;
183 } while (va < last_va);
184
185 DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
186 return true;
187 } else {
188 TlbEntry entry;
189 //Check to make sure the first byte is mapped into the processes address
190 //space.
191 if (context->getProcessPtr()->pTable->lookup(va, entry))
192 return true;
193 return false;
194 }
195}
196
197/*
198 * Translate the kernel debugger register format into the GDB register
199 * format.
200 */
201void
202RemoteGDB::getregs()
203{
204 DPRINTF(GDBAcc, "getregs in remotegdb \n");
205
206 memset(gdbregs.regs, 0, gdbregs.bytes());
207
208 if (inAArch64(context)) { // AArch64
209 // x0-x31
210 for (int i = 0; i < 32; ++i) {
211 gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i);
212 }
213 // pc
214 gdbregs.regs[REG_PC_64] = context->pcState().pc();
215 // cpsr
216 gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR);
217 // v0-v31
218 for (int i = 0; i < 32; ++i) {
219 gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>(
220 context->readFloatRegBits(i * 4 + 3)) << 32 |
221 context->readFloatRegBits(i * 4 + 2);
222 gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>(
223 context->readFloatRegBits(i * 4 + 1)) << 32 |
224 context->readFloatRegBits(i * 4 + 0);
225 }
226 } else { // AArch32
227 // R0-R15 supervisor mode
228 // arm registers are 32 bits wide, gdb registers are 64 bits wide two
229 // arm registers are packed into one gdb register (little endian)
230 gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 |
231 context->readIntReg(INTREG_R0);
232 gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 |
233 context->readIntReg(INTREG_R2);
234 gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 |
235 context->readIntReg(INTREG_R4);
236 gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 |
237 context->readIntReg(INTREG_R6);
238 gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 |
239 context->readIntReg(INTREG_R8);
240 gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32|
241 context->readIntReg(INTREG_R10);
242 gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 |
243 context->readIntReg(INTREG_R12);
244 gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 |
245 context->readIntReg(INTREG_LR);
246
247 // CPSR
248 gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
249
250 // vfpv3/neon floating point registers (32 double or 64 float)
251
252 gdbregs.regs[REG_F0] =
253 static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 |
254 gdbregs.regs[REG_CPSR];
255
256 for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) {
257 gdbregs.regs[i + REG_F0] =
258 static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 |
259 context->readFloatRegBits(2*i-1);
260 }
261
262 // FPSCR
263 gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>(
264 context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 |
265 context->readFloatRegBits(NumFloatV7ArchRegs - 1);
266 }
267}
268
269/*
270 * Translate the GDB register format into the kernel debugger register
271 * format.
272 */
273void
274RemoteGDB::setregs()
275{
276
277 DPRINTF(GDBAcc, "setregs in remotegdb \n");
278 if (inAArch64(context)) { // AArch64
279 // x0-x31
280 for (int i = 0; i < 32; ++i) {
281 context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]);
282 }
283 // pc
284 context->pcState(gdbregs.regs[REG_PC_64]);
285 // cpsr
286 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]);
287 // v0-v31
288 for (int i = 0; i < 32; ++i) {
289 context->setFloatRegBits(i * 4 + 3,
290 gdbregs.regs[REG_V0 + 2 * i] >> 32);
291 context->setFloatRegBits(i * 4 + 2,
292 gdbregs.regs[REG_V0 + 2 * i]);
293 context->setFloatRegBits(i * 4 + 1,
294 gdbregs.regs[REG_V0 + 2 * i + 1] >> 32);
295 context->setFloatRegBits(i * 4 + 0,
296 gdbregs.regs[REG_V0 + 2 * i + 1]);
297 }
298 } else { // AArch32
299 // R0-R15 supervisor mode
300 // arm registers are 32 bits wide, gdb registers are 64 bits wide
301 // two arm registers are packed into one gdb register (little endian)
302 context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0));
303 context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32));
304 context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0));
305 context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32));
306 context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0));
307 context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32));
308 context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0));
309 context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32));
310 context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0));
311 context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32));
312 context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0));
313 context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32));
314 context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0));
315 context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32));
316 context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0));
317 context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32));
318
319 //CPSR
320 context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]);
321
322 //vfpv3/neon floating point registers (32 double or 64 float)
323 context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32);
324
325 for (int i = 1; i < NumFloatV7ArchRegs; ++i) {
326 if (i%2) {
327 int j = (i+1)/2;
328 context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0));
329 } else {
330 int j = i/2;
331 context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32);
332 }
333 }
334
335 //FPSCR
336 context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
337 }
338}
339
340void
341RemoteGDB::clearSingleStep()
342{
343 DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
344 takenBkpt, notTakenBkpt);
345
346 if (takenBkpt != 0)
347 clearTempBreakpoint(takenBkpt);
348
349 if (notTakenBkpt != 0)
350 clearTempBreakpoint(notTakenBkpt);
351}
352
353void
354RemoteGDB::setSingleStep()
355{
356 PCState pc = context->pcState();
357 PCState bpc;
358 bool set_bt = false;
359
360 // User was stopped at pc, e.g. the instruction at pc was not
361 // executed.
362 MachInst inst = read<MachInst>(pc.pc());
363 StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc());
364 if (si->hasBranchTarget(pc, context, bpc)) {
365 // Don't bother setting a breakpoint on the taken branch if it
366 // is the same as the next pc
367 if (bpc.pc() != pc.npc())
368 set_bt = true;
369 }
370
371 DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n",
372 takenBkpt, notTakenBkpt);
373
374 setTempBreakpoint(notTakenBkpt = pc.npc());
375
376 if (set_bt)
377 setTempBreakpoint(takenBkpt = bpc.pc());
378}
379
380// Write bytes to kernel address space for debugger.
381bool
382RemoteGDB::write(Addr vaddr, size_t size, const char *data)
383{
384 return BaseRemoteGDB::write(vaddr, size, data);
385}
386
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