registers.hh (9918:2c7219e2d999) | registers.hh (9920:028e4da64b42) |
---|---|
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63 64// floating point register file entry type 65typedef uint32_t FloatRegBits; 66typedef float FloatReg; 67 68// cop-0/cop-1 system control register 69typedef uint64_t MiscReg; 70 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63 64// floating point register file entry type 65typedef uint32_t FloatRegBits; 66typedef float FloatReg; 67 68// cop-0/cop-1 system control register 69typedef uint64_t MiscReg; 70 |
71// dummy typedef since we don't have CC regs 72typedef uint8_t CCReg; 73 |
|
71// Constants Related to the number of registers 72const int NumIntArchRegs = NUM_ARCH_INTREGS; 73// The number of single precision floating point registers 74const int NumFloatArchRegs = 64; 75const int NumFloatSpecialRegs = 8; 76 77const int NumIntRegs = NUM_INTREGS; 78const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; | 74// Constants Related to the number of registers 75const int NumIntArchRegs = NUM_ARCH_INTREGS; 76// The number of single precision floating point registers 77const int NumFloatArchRegs = 64; 78const int NumFloatSpecialRegs = 8; 79 80const int NumIntRegs = NUM_INTREGS; 81const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; |
82const int NumCCRegs = 0; |
|
79const int NumMiscRegs = NUM_MISCREGS; 80 81const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 82 83// semantically meaningful register indices 84const int ReturnValueReg = 0; 85const int ReturnValueReg1 = 1; 86const int ReturnValueReg2 = 2; --- 10 unchanged lines hidden (view full) --- 97const int ZeroReg = INTREG_ZERO; 98 99const int SyscallNumReg = ReturnValueReg; 100const int SyscallPseudoReturnReg = ReturnValueReg; 101const int SyscallSuccessReg = ReturnValueReg; 102 103// These help enumerate all the registers for dependence tracking. 104const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); | 83const int NumMiscRegs = NUM_MISCREGS; 84 85const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 86 87// semantically meaningful register indices 88const int ReturnValueReg = 0; 89const int ReturnValueReg1 = 1; 90const int ReturnValueReg2 = 2; --- 10 unchanged lines hidden (view full) --- 101const int ZeroReg = INTREG_ZERO; 102 103const int SyscallNumReg = ReturnValueReg; 104const int SyscallPseudoReturnReg = ReturnValueReg; 105const int SyscallSuccessReg = ReturnValueReg; 106 107// These help enumerate all the registers for dependence tracking. 108const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); |
105const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs; | 109const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 110const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 |
106const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 107 108typedef union { 109 IntReg intreg; 110 FloatReg fpreg; 111 MiscReg ctrlreg; 112} AnyReg; 113 114} // namespace ArmISA 115 116#endif | 111const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 112 113typedef union { 114 IntReg intreg; 115 FloatReg fpreg; 116 MiscReg ctrlreg; 117} AnyReg; 118 119} // namespace ArmISA 120 121#endif |