registers.hh (8229:78bf55f23338) registers.hh (8961:ff4762285f99)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/generated/max_inst_regs.hh"
46#include "arch/arm/intregs.hh"
47#include "arch/arm/intregs.hh"
47#include "arch/arm/max_inst_regs.hh"
48#include "arch/arm/miscregs.hh"
49
50namespace ArmISA {
51
52
53// For a predicated instruction, we need all the
54// destination registers to also be sources
55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +

--- 60 unchanged lines hidden --- 		48#include "arch/arm/miscregs.hh"
49
50namespace ArmISA {
51
52
53// For a predicated instruction, we need all the
54// destination registers to also be sources
55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +

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