registers.hh (14091:090449e74135) registers.hh (14106:293e3f4b1321)
1/*
2 * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80// The number of single precision floating point registers
81const int NumFloatV7ArchRegs = 64;
82const int NumFloatV8ArchRegs = 128;
83const int NumFloatSpecialRegs = 32;
84const int NumVecV7ArchRegs = 64;
85const int NumVecV8ArchRegs = 32;
86const int NumVecSpecialRegs = 8;
87
1/*
2 * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 71 unchanged lines hidden (view full) ---

80// The number of single precision floating point registers
81const int NumFloatV7ArchRegs = 64;
82const int NumFloatV8ArchRegs = 128;
83const int NumFloatSpecialRegs = 32;
84const int NumVecV7ArchRegs = 64;
85const int NumVecV8ArchRegs = 32;
86const int NumVecSpecialRegs = 8;
87
88const int NumVecIntrlvRegs = 4;
88const int NumIntRegs = NUM_INTREGS;
89const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
89const int NumIntRegs = NUM_INTREGS;
90const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
90const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
91const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
91const int VECREG_UREG0 = 32;
92const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
93const int PREDREG_FFR = 16;
94const int PREDREG_UREG0 = 17;
95const int NumCCRegs = NUM_CCREGS;
96const int NumMiscRegs = NUM_MISCREGS;
92const int VECREG_UREG0 = 32;
93const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
94const int PREDREG_FFR = 16;
95const int PREDREG_UREG0 = 17;
96const int NumCCRegs = NUM_CCREGS;
97const int NumMiscRegs = NUM_MISCREGS;
98const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
99const int INTRLVREG1 = INTRLVREG0 + 1;
100const int INTRLVREG2 = INTRLVREG0 + 2;
101const int INTRLVREG3 = INTRLVREG0 + 3;
97
98#define ISA_HAS_CC_REGS
99
100const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
101 NumVecPredRegs + NumMiscRegs;
102
103// semantically meaningful register indices
104const int ReturnValueReg = 0;

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103#define ISA_HAS_CC_REGS
104
105const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
106 NumVecPredRegs + NumMiscRegs;
107
108// semantically meaningful register indices
109const int ReturnValueReg = 0;

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