registers.hh (13581:b6dcd0183747) registers.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/ccregs.hh"
47#include "arch/arm/generated/max_inst_regs.hh"
48#include "arch/arm/intregs.hh"
49#include "arch/arm/miscregs.hh"
1/*
2 * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/ccregs.hh"
47#include "arch/arm/generated/max_inst_regs.hh"
48#include "arch/arm/intregs.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "arch/generic/vec_pred_reg.hh"
50#include "arch/generic/vec_reg.hh"
51
52namespace ArmISA {
53
54
55// For a predicated instruction, we need all the
56// destination registers to also be sources
57const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
58 ArmISAInst::MaxInstSrcRegs;
59using ArmISAInst::MaxInstDestRegs;
60using ArmISAInst::MaxMiscDestRegs;
61
62// Number of VecElem per Vector Register, computed based on the vector length
63constexpr unsigned NumVecElemPerVecReg = 4;
64using VecElem = uint32_t;
65using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
66using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
67using VecRegContainer = VecReg::Container;
68
52#include "arch/generic/vec_reg.hh"
53
54namespace ArmISA {
55
56
57// For a predicated instruction, we need all the
58// destination registers to also be sources
59const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
60 ArmISAInst::MaxInstSrcRegs;
61using ArmISAInst::MaxInstDestRegs;
62using ArmISAInst::MaxMiscDestRegs;
63
64// Number of VecElem per Vector Register, computed based on the vector length
65constexpr unsigned NumVecElemPerVecReg = 4;
66using VecElem = uint32_t;
67using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
68using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
69using VecRegContainer = VecReg::Container;
70
71constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
72
73// Dummy typedefs
74using VecPredReg = ::DummyVecPredReg;
75using ConstVecPredReg = ::DummyConstVecPredReg;
76using VecPredRegContainer = ::DummyVecPredRegContainer;
77constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
78constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
79
69// condition code register; must be at least 32 bits for FpCondCodes
70typedef uint64_t CCReg;
71
72// Constants Related to the number of registers
73const int NumIntArchRegs = NUM_ARCH_INTREGS;
74// The number of single precision floating point registers
75const int NumFloatV7ArchRegs = 64;
76const int NumFloatV8ArchRegs = 128;
77const int NumFloatSpecialRegs = 32;
78const int NumVecV7ArchRegs = 64;
79const int NumVecV8ArchRegs = 32;
80const int NumVecSpecialRegs = 8;
81
82const int NumIntRegs = NUM_INTREGS;
83const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
84const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
80// condition code register; must be at least 32 bits for FpCondCodes
81typedef uint64_t CCReg;
82
83// Constants Related to the number of registers
84const int NumIntArchRegs = NUM_ARCH_INTREGS;
85// The number of single precision floating point registers
86const int NumFloatV7ArchRegs = 64;
87const int NumFloatV8ArchRegs = 128;
88const int NumFloatSpecialRegs = 32;
89const int NumVecV7ArchRegs = 64;
90const int NumVecV8ArchRegs = 32;
91const int NumVecSpecialRegs = 8;
92
93const int NumIntRegs = NUM_INTREGS;
94const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
95const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
96const int NumVecPredRegs = 1;
85const int NumCCRegs = NUM_CCREGS;
86const int NumMiscRegs = NUM_MISCREGS;
87
88#define ISA_HAS_CC_REGS
89
97const int NumCCRegs = NUM_CCREGS;
98const int NumMiscRegs = NUM_MISCREGS;
99
100#define ISA_HAS_CC_REGS
101
90const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs;
102const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
103 NumVecPredRegs + NumMiscRegs;
91
92// semantically meaningful register indices
93const int ReturnValueReg = 0;
94const int ReturnValueReg1 = 1;
95const int ReturnValueReg2 = 2;
96const int NumArgumentRegs = 4;
97const int NumArgumentRegs64 = 8;
98const int ArgumentReg0 = 0;

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105// semantically meaningful register indices
106const int ReturnValueReg = 0;
107const int ReturnValueReg1 = 1;
108const int ReturnValueReg2 = 2;
109const int NumArgumentRegs = 4;
110const int NumArgumentRegs64 = 8;
111const int ArgumentReg0 = 0;

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