registers.hh (13556:9f57bb56153a) registers.hh (13581:b6dcd0183747)
1/*
2 * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 45 unchanged lines hidden (view full) ---

54
55// For a predicated instruction, we need all the
56// destination registers to also be sources
57const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
58 ArmISAInst::MaxInstSrcRegs;
59using ArmISAInst::MaxInstDestRegs;
60using ArmISAInst::MaxMiscDestRegs;
61
1/*
2 * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 45 unchanged lines hidden (view full) ---

54
55// For a predicated instruction, we need all the
56// destination registers to also be sources
57const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
58 ArmISAInst::MaxInstSrcRegs;
59using ArmISAInst::MaxInstDestRegs;
60using ArmISAInst::MaxMiscDestRegs;
61
62typedef RegVal IntReg;
63
64// floating point register file entry type
65typedef RegVal FloatRegBits;
66typedef FloatRegVal FloatReg;
67
68// Number of VecElem per Vector Register, computed based on the vector length
69constexpr unsigned NumVecElemPerVecReg = 4;
70using VecElem = uint32_t;
71using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
72using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
73using VecRegContainer = VecReg::Container;
74
62// Number of VecElem per Vector Register, computed based on the vector length
63constexpr unsigned NumVecElemPerVecReg = 4;
64using VecElem = uint32_t;
65using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
66using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
67using VecRegContainer = VecReg::Container;
68
75// cop-0/cop-1 system control register
76typedef RegVal MiscReg;
77
78// condition code register; must be at least 32 bits for FpCondCodes
79typedef uint64_t CCReg;
80
81// Constants Related to the number of registers
82const int NumIntArchRegs = NUM_ARCH_INTREGS;
83// The number of single precision floating point registers
84const int NumFloatV7ArchRegs = 64;
85const int NumFloatV8ArchRegs = 128;

--- 39 unchanged lines hidden --- 		69// condition code register; must be at least 32 bits for FpCondCodes
70typedef uint64_t CCReg;
71
72// Constants Related to the number of registers
73const int NumIntArchRegs = NUM_ARCH_INTREGS;
74// The number of single precision floating point registers
75const int NumFloatV7ArchRegs = 64;
76const int NumFloatV8ArchRegs = 128;

--- 39 unchanged lines hidden ---