registers.hh (10934:5af8f40d8f2c) | registers.hh (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2010-2011, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 58 unchanged lines hidden (view full) --- 67typedef float FloatReg; 68 69// cop-0/cop-1 system control register 70typedef uint64_t MiscReg; 71 72// condition code register; must be at least 32 bits for FpCondCodes 73typedef uint64_t CCReg; 74 | 1/* 2 * Copyright (c) 2010-2011, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 58 unchanged lines hidden (view full) --- 67typedef float FloatReg; 68 69// cop-0/cop-1 system control register 70typedef uint64_t MiscReg; 71 72// condition code register; must be at least 32 bits for FpCondCodes 73typedef uint64_t CCReg; 74 |
75// vector register file entry type 76typedef uint64_t VectorRegElement; 77const int NumVectorRegElements = 0; 78const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); 79typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; 80 | |
81// Constants Related to the number of registers 82const int NumIntArchRegs = NUM_ARCH_INTREGS; 83// The number of single precision floating point registers 84const int NumFloatV7ArchRegs = 64; 85const int NumFloatV8ArchRegs = 128; 86const int NumFloatSpecialRegs = 32; 87 88const int NumIntRegs = NUM_INTREGS; 89const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 90const int NumCCRegs = NUM_CCREGS; | 75// Constants Related to the number of registers 76const int NumIntArchRegs = NUM_ARCH_INTREGS; 77// The number of single precision floating point registers 78const int NumFloatV7ArchRegs = 64; 79const int NumFloatV8ArchRegs = 128; 80const int NumFloatSpecialRegs = 32; 81 82const int NumIntRegs = NUM_INTREGS; 83const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 84const int NumCCRegs = NUM_CCREGS; |
91const int NumVectorRegs = 0; | |
92const int NumMiscRegs = NUM_MISCREGS; 93 94#define ISA_HAS_CC_REGS 95 96const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 97 98// semantically meaningful register indices 99const int ReturnValueReg = 0; --- 14 unchanged lines hidden (view full) --- 114 115const int SyscallNumReg = ReturnValueReg; 116const int SyscallPseudoReturnReg = ReturnValueReg; 117const int SyscallSuccessReg = ReturnValueReg; 118 119// These help enumerate all the registers for dependence tracking. 120const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 121const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; | 85const int NumMiscRegs = NUM_MISCREGS; 86 87#define ISA_HAS_CC_REGS 88 89const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 90 91// semantically meaningful register indices 92const int ReturnValueReg = 0; --- 14 unchanged lines hidden (view full) --- 107 108const int SyscallNumReg = ReturnValueReg; 109const int SyscallPseudoReturnReg = ReturnValueReg; 110const int SyscallSuccessReg = ReturnValueReg; 111 112// These help enumerate all the registers for dependence tracking. 113const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 114const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; |
122const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; 123const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; | 115const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; |
124const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 125 126typedef union { 127 IntReg intreg; 128 FloatReg fpreg; 129 CCReg ccreg; 130 MiscReg ctrlreg; 131} AnyReg; 132 133} // namespace ArmISA 134 135#endif | 116const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 117 118typedef union { 119 IntReg intreg; 120 FloatReg fpreg; 121 CCReg ccreg; 122 MiscReg ctrlreg; 123} AnyReg; 124 125} // namespace ArmISA 126 127#endif |