registers.hh (10037:5cac77888310) | registers.hh (10338:8bee5f4edb92) |
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1/* | 1/* |
2 * Copyright (c) 2010-2011 ARM Limited | 2 * Copyright (c) 2010-2011, 2014 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 29 unchanged lines hidden (view full) --- 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/generated/max_inst_regs.hh" 47#include "arch/arm/intregs.hh" | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 29 unchanged lines hidden (view full) --- 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/generated/max_inst_regs.hh" 47#include "arch/arm/intregs.hh" |
48#include "arch/arm/ccregs.hh" |
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48#include "arch/arm/miscregs.hh" 49 50namespace ArmISA { 51 52 53// For a predicated instruction, we need all the 54// destination registers to also be sources 55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + --- 7 unchanged lines hidden (view full) --- 63 64// floating point register file entry type 65typedef uint32_t FloatRegBits; 66typedef float FloatReg; 67 68// cop-0/cop-1 system control register 69typedef uint64_t MiscReg; 70 | 49#include "arch/arm/miscregs.hh" 50 51namespace ArmISA { 52 53 54// For a predicated instruction, we need all the 55// destination registers to also be sources 56const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + --- 7 unchanged lines hidden (view full) --- 64 65// floating point register file entry type 66typedef uint32_t FloatRegBits; 67typedef float FloatReg; 68 69// cop-0/cop-1 system control register 70typedef uint64_t MiscReg; 71 |
71// dummy typedef since we don't have CC regs 72typedef uint8_t CCReg; | 72// condition code register; must be at least 32 bits for FpCondCodes 73typedef uint64_t CCReg; |
73 74// Constants Related to the number of registers 75const int NumIntArchRegs = NUM_ARCH_INTREGS; 76// The number of single precision floating point registers 77const int NumFloatV7ArchRegs = 64; 78const int NumFloatV8ArchRegs = 128; 79const int NumFloatSpecialRegs = 32; 80 81const int NumIntRegs = NUM_INTREGS; 82const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; | 74 75// Constants Related to the number of registers 76const int NumIntArchRegs = NUM_ARCH_INTREGS; 77// The number of single precision floating point registers 78const int NumFloatV7ArchRegs = 64; 79const int NumFloatV8ArchRegs = 128; 80const int NumFloatSpecialRegs = 32; 81 82const int NumIntRegs = NUM_INTREGS; 83const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; |
83const int NumCCRegs = 0; | 84const int NumCCRegs = NUM_CCREGS; |
84const int NumMiscRegs = NUM_MISCREGS; 85 | 85const int NumMiscRegs = NUM_MISCREGS; 86 |
87#define ISA_HAS_CC_REGS 88 |
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86const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 87 88// semantically meaningful register indices 89const int ReturnValueReg = 0; 90const int ReturnValueReg1 = 1; 91const int ReturnValueReg2 = 2; 92const int NumArgumentRegs = 4; 93const int NumArgumentRegs64 = 8; --- 10 unchanged lines hidden (view full) --- 104 105const int SyscallNumReg = ReturnValueReg; 106const int SyscallPseudoReturnReg = ReturnValueReg; 107const int SyscallSuccessReg = ReturnValueReg; 108 109// These help enumerate all the registers for dependence tracking. 110const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 111const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; | 89const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 90 91// semantically meaningful register indices 92const int ReturnValueReg = 0; 93const int ReturnValueReg1 = 1; 94const int ReturnValueReg2 = 2; 95const int NumArgumentRegs = 4; 96const int NumArgumentRegs64 = 8; --- 10 unchanged lines hidden (view full) --- 107 108const int SyscallNumReg = ReturnValueReg; 109const int SyscallPseudoReturnReg = ReturnValueReg; 110const int SyscallSuccessReg = ReturnValueReg; 111 112// These help enumerate all the registers for dependence tracking. 113const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 114const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; |
112const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 | 115const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; |
113const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 114 115typedef union { 116 IntReg intreg; 117 FloatReg fpreg; | 116const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 117 118typedef union { 119 IntReg intreg; 120 FloatReg fpreg; |
121 CCReg ccreg; |
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118 MiscReg ctrlreg; 119} AnyReg; 120 121} // namespace ArmISA 122 123#endif | 122 MiscReg ctrlreg; 123} AnyReg; 124 125} // namespace ArmISA 126 127#endif |