1/*
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2 * Copyright (c) 2010 ARM Limited
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2 * Copyright (c) 2010-2011 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/generated/max_inst_regs.hh" 47#include "arch/arm/intregs.hh" 48#include "arch/arm/miscregs.hh" 49 50namespace ArmISA { 51 52 53// For a predicated instruction, we need all the 54// destination registers to also be sources 55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 56 ArmISAInst::MaxInstSrcRegs; 57using ArmISAInst::MaxInstDestRegs; 58using ArmISAInst::MaxMiscDestRegs; 59 60typedef uint16_t RegIndex; 61 62typedef uint64_t IntReg; 63 64// floating point register file entry type 65typedef uint32_t FloatRegBits; 66typedef float FloatReg; 67 68// cop-0/cop-1 system control register 69typedef uint64_t MiscReg; 70 71// dummy typedef since we don't have CC regs 72typedef uint8_t CCReg; 73 74// Constants Related to the number of registers 75const int NumIntArchRegs = NUM_ARCH_INTREGS; 76// The number of single precision floating point registers
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77const int NumFloatArchRegs = 64;
78const int NumFloatSpecialRegs = 8;
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77const int NumFloatV7ArchRegs = 64; 78const int NumFloatV8ArchRegs = 128; 79const int NumFloatSpecialRegs = 32; |
80 81const int NumIntRegs = NUM_INTREGS;
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81const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
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82const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; |
83const int NumCCRegs = 0; 84const int NumMiscRegs = NUM_MISCREGS; 85 86const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 87 88// semantically meaningful register indices 89const int ReturnValueReg = 0; 90const int ReturnValueReg1 = 1; 91const int ReturnValueReg2 = 2; 92const int NumArgumentRegs = 4;
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93const int NumArgumentRegs64 = 8; |
94const int ArgumentReg0 = 0; 95const int ArgumentReg1 = 1; 96const int ArgumentReg2 = 2; 97const int ArgumentReg3 = 3; 98const int FramePointerReg = 11; 99const int StackPointerReg = INTREG_SP; 100const int ReturnAddressReg = INTREG_LR; 101const int PCReg = INTREG_PC; 102 103const int ZeroReg = INTREG_ZERO; 104 105const int SyscallNumReg = ReturnValueReg; 106const int SyscallPseudoReturnReg = ReturnValueReg; 107const int SyscallSuccessReg = ReturnValueReg; 108 109// These help enumerate all the registers for dependence tracking. 110const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 111const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 112const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 113const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 114 115typedef union { 116 IntReg intreg; 117 FloatReg fpreg; 118 MiscReg ctrlreg; 119} AnyReg; 120 121} // namespace ArmISA 122 123#endif
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