1/* |
2 * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 45 unchanged lines hidden (view full) --- 56 57// For a predicated instruction, we need all the 58// destination registers to also be sources 59const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 60 ArmISAInst::MaxInstSrcRegs; 61using ArmISAInst::MaxInstDestRegs; 62using ArmISAInst::MaxMiscDestRegs; 63 |
64// Number of VecElem per Vector Register considering only pre-SVE 65// Advanced SIMD registers. 66constexpr unsigned NumVecElemPerNeonVecReg = 4; |
67// Number of VecElem per Vector Register, computed based on the vector length 68constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords; 69 70using VecElem = uint32_t; 71using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 72using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 73using VecRegContainer = VecReg::Container; 74 --- 60 unchanged lines hidden --- |