1/* |
2 * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 73 unchanged lines hidden (view full) --- 84const int NumVecV7ArchRegs = 64; 85const int NumVecV8ArchRegs = 32; 86const int NumVecSpecialRegs = 8; 87 88const int NumIntRegs = NUM_INTREGS; 89const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 90const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; 91const int VECREG_UREG0 = 32; |
92const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0 |
93const int PREDREG_FFR = 16; |
94const int PREDREG_UREG0 = 17; |
95const int NumCCRegs = NUM_CCREGS; 96const int NumMiscRegs = NUM_MISCREGS; 97 98#define ISA_HAS_CC_REGS 99 100const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + 101 NumVecPredRegs + NumMiscRegs; 102 --- 24 unchanged lines hidden --- |