1/*
2 * Copyright (c) 2010-2011, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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67typedef float FloatReg;
68
69// cop-0/cop-1 system control register
70typedef uint64_t MiscReg;
71
72// condition code register; must be at least 32 bits for FpCondCodes
73typedef uint64_t CCReg;
74
75// Constants Related to the number of registers
76const int NumIntArchRegs = NUM_ARCH_INTREGS;
77// The number of single precision floating point registers
78const int NumFloatV7ArchRegs = 64;
79const int NumFloatV8ArchRegs = 128;
80const int NumFloatSpecialRegs = 32;
81
82const int NumIntRegs = NUM_INTREGS;
83const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
84const int NumCCRegs = NUM_CCREGS;
85const int NumMiscRegs = NUM_MISCREGS;
86
87#define ISA_HAS_CC_REGS
88
89const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
90
91// semantically meaningful register indices
92const int ReturnValueReg = 0;

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107
108const int SyscallNumReg = ReturnValueReg;
109const int SyscallPseudoReturnReg = ReturnValueReg;
110const int SyscallSuccessReg = ReturnValueReg;
111
112// These help enumerate all the registers for dependence tracking.
113const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
114const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
115const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
116const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
117
118typedef union {
119 IntReg intreg;
120 FloatReg fpreg;
121 CCReg ccreg;
122 MiscReg ctrlreg;
123} AnyReg;
124
125} // namespace ArmISA
126
127#endif