process.cc (13122:32e21edd0a61) process.cc (13581:b6dcd0183747)
1/*
2 * Copyright (c) 2010, 2012, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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477 pc.nextAArch64(pc.aarch64());
478 pc.set(getStartPC() & ~mask(1));
479 tc->pcState(pc);
480
481 //Align the "stackMin" to a page boundary.
482 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
483}
484
1/*
2 * Copyright (c) 2010, 2012, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 468 unchanged lines hidden (view full) ---

477 pc.nextAArch64(pc.aarch64());
478 pc.set(getStartPC() & ~mask(1));
479 tc->pcState(pc);
480
481 //Align the "stackMin" to a page boundary.
482 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
483}
484
485ArmISA::IntReg
485RegVal
486ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
487{
488 assert(i < 6);
489 return tc->readIntReg(ArgumentReg0 + i++);
490}
491
486ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
487{
488 assert(i < 6);
489 return tc->readIntReg(ArgumentReg0 + i++);
490}
491
492ArmISA::IntReg
492RegVal
493ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
494{
495 assert(i < 8);
496 return tc->readIntReg(ArgumentReg0 + i++);
497}
498
493ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
494{
495 assert(i < 8);
496 return tc->readIntReg(ArgumentReg0 + i++);
497}
498
499ArmISA::IntReg
499RegVal
500ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
501{
502 assert(width == 32 || width == 64);
503 if (width == 32)
504 return getSyscallArg(tc, i);
505
506 // 64 bit arguments are passed starting in an even register
507 if (i % 2 != 0)
508 i++;
509
510 // Registers r0-r6 can be used
511 assert(i < 5);
512 uint64_t val;
513 val = tc->readIntReg(ArgumentReg0 + i++);
514 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
515 return val;
516}
517
500ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
501{
502 assert(width == 32 || width == 64);
503 if (width == 32)
504 return getSyscallArg(tc, i);
505
506 // 64 bit arguments are passed starting in an even register
507 if (i % 2 != 0)
508 i++;
509
510 // Registers r0-r6 can be used
511 assert(i < 5);
512 uint64_t val;
513 val = tc->readIntReg(ArgumentReg0 + i++);
514 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
515 return val;
516}
517
518ArmISA::IntReg
518RegVal
519ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
520{
521 return getSyscallArg(tc, i);
522}
523
524
525void
519ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
520{
521 return getSyscallArg(tc, i);
522}
523
524
525void
526ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
526ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val)
527{
528 assert(i < 6);
529 tc->setIntReg(ArgumentReg0 + i, val);
530}
531
532void
527{
528 assert(i < 6);
529 tc->setIntReg(ArgumentReg0 + i, val);
530}
531
532void
533ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
533ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
534{
535 assert(i < 8);
536 tc->setIntReg(ArgumentReg0 + i, val);
537}
538
539void
540ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
541{

--- 30 unchanged lines hidden --- 		534{
535 assert(i < 8);
536 tc->setIntReg(ArgumentReg0 + i, val);
537}
538
539void
540ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
541{

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