1/* |
2 * Copyright (c) 2010, 2012, 2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 126 unchanged lines hidden (view full) --- 137 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 138 // Generically enable floating point support. 139 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 140 fpexc.en = 1; 141 tc->setMiscReg(MISCREG_FPEXC, fpexc); 142 } 143} 144 |
145uint32_t 146ArmProcess32::armHwcapImpl() const 147{ 148 enum ArmCpuFeature { 149 Arm_Swp = 1 << 0, 150 Arm_Half = 1 << 1, 151 Arm_Thumb = 1 << 2, 152 Arm_26Bit = 1 << 3, 153 Arm_FastMult = 1 << 4, 154 Arm_Fpa = 1 << 5, 155 Arm_Vfp = 1 << 6, 156 Arm_Edsp = 1 << 7, 157 Arm_Java = 1 << 8, 158 Arm_Iwmmxt = 1 << 9, 159 Arm_Crunch = 1 << 10, 160 Arm_ThumbEE = 1 << 11, 161 Arm_Neon = 1 << 12, 162 Arm_Vfpv3 = 1 << 13, 163 Arm_Vfpv3d16 = 1 << 14 164 }; 165 166 return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult | 167 Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon | 168 Arm_Vfpv3 | Arm_Vfpv3d16; 169} 170 171uint32_t 172ArmProcess64::armHwcapImpl() const 173{ 174 // In order to know what these flags mean, please refer to Linux 175 // /Documentation/arm64/elf_hwcaps.txt text file. 176 enum ArmCpuFeature { 177 Arm_Fp = 1 << 0, 178 Arm_Asimd = 1 << 1, 179 Arm_Evtstrm = 1 << 2, 180 Arm_Aes = 1 << 3, 181 Arm_Pmull = 1 << 4, 182 Arm_Sha1 = 1 << 5, 183 Arm_Sha2 = 1 << 6, 184 Arm_Crc32 = 1 << 7, 185 Arm_Atomics = 1 << 8, 186 Arm_Fphp = 1 << 9, 187 Arm_Asimdhp = 1 << 10, 188 Arm_Cpuid = 1 << 11, 189 Arm_Asimdrdm = 1 << 12, 190 Arm_Jscvt = 1 << 13, 191 Arm_Fcma = 1 << 14, 192 Arm_Lrcpc = 1 << 15, 193 Arm_Dcpop = 1 << 16, 194 Arm_Sha3 = 1 << 17, 195 Arm_Sm3 = 1 << 18, 196 Arm_Sm4 = 1 << 19, 197 Arm_Asimddp = 1 << 20, 198 Arm_Sha512 = 1 << 21, 199 Arm_Sve = 1 << 22, 200 Arm_Asimdfhm = 1 << 23, 201 Arm_Dit = 1 << 24, 202 Arm_Uscat = 1 << 25, 203 Arm_Ilrcpc = 1 << 26, 204 Arm_Flagm = 1 << 27 205 }; 206 207 return Arm_Fp | Arm_Asimd | Arm_Evtstrm | Arm_Crc32; 208} 209 |
210template <class IntType> 211void 212ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 213{ 214 int intSize = sizeof(IntType); 215 216 typedef AuxVector<IntType> auxv_t; 217 std::vector<auxv_t> auxv; --- 8 unchanged lines hidden (view full) --- 226 uint64_t align = 16; 227 228 // Patch the ld_bias for dynamic executables. 229 updateBias(); 230 231 // load object file into target memory 232 objFile->loadSections(initVirtMem); 233 |
234 //Setup the auxilliary vectors. These will already have endian conversion. 235 //Auxilliary vectors are loaded only for elf formatted executables. 236 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 237 if (elfObject) { 238 239 if (objFile->getOpSys() == ObjectFile::Linux) { |
240 IntType features = armHwcap<IntType>(); |
241 242 //Bits which describe the system hardware capabilities 243 //XXX Figure out what these should be 244 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 245 //Frequency at which times() increments 246 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 247 //Whether to enable "secure mode" in the executable 248 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); --- 281 unchanged lines hidden --- |